Senior Staff Engineer - SOC Static Timing Analysis (STA)

About Synopsys

Synopsys drives innovation shaping modern connectivity and intelligent devices. Central to the era of pervasive intelligence, our technology spans self-driving cars to learning machines, excelling in chip design, verification, and IP integration to enable high-performance silicon and software solutions. Join us to lead continuous tech innovation shaping the future.

Role Overview

We seek a passionate and execution-oriented Senior Staff Engineer experienced in Static Timing Analysis (STA), specializing in timing closure and signoff techniques for advanced semiconductor nodes (16/12/10/7nm; experience with 5nm advantageous). You will manage block-level timing deliverables, contribute to full-chip closure, collaborate across physical design, synthesis, and verification teams, and apply your deep knowledge to solve tough timing challenges under tight schedules.

Key Responsibilities

• Lead block-level STA signoff and contribute to comprehensive chip timing closure for cutting-edge nodes.
• Troubleshoot and resolve timing closure issues (setup/hold, recovery/removal, clock gating, CDC assumptions) collaborating with design and physical design teams.
• Create, validate, and maintain timing constraints (SDC) involving clocks, generated clocks, exceptions, IO constraints, and covering all modes and corners.
• Conduct power signoff and support analyses using PrimePower and PT-PX tools, understanding timing and power impacts of design changes.
• Support timing and power ECO development and verification through signoff checks and regression testing.
• Coordinate with synthesis and implementation teams to ensure alignment on timing constraints and interpretation of physical effects such as parasitics and derates.
• Utilize Synopsys toolset including PrimeTime, PrimePower/PT-PX, and PrimeClosure/Tweaker to meet power, performance, and area (PPA) targets.
• Develop and maintain automation scripts in TCL, Python, and Perl to boost STA productivity, improve reporting, and support regression quality.
• Enhance STA methodologies, maintain checklists, implement best practices, and mentor junior engineers informally as needed.

Qualifications and Experience

• Bachelor's or Master's degree in Electronics, Electrical Engineering, or a related technical discipline.
• Minimum 8 years of STA and timing closure experience with direct responsibility for block-level ownership; experience with full-chip timing closure preferred.
• Expertise in constraints development and validation (SDC).
• Proficient in STA signoff methods across multiple modes and corners, including MMMC concepts.
• Strong skills in timing closure debugging and ECO validation processes.
• Experience with power analysis and support tools such as PrimePower or PT-PX.
• Hands-on experience with Synopsys PrimeTime is essential; working knowledge of PrimePower/PT-PX, PrimeClosure, and Tweaker is desirable.
• Familiarity with Fusion Compiler/ICC2 or Design Compiler, parasitic extraction tools like StarRC, and signoff correlation techniques driven by these tools is preferred.
• Advanced scripting ability in TCL (required), with proficiency in Python and Perl highly valuable.
• Understanding of low-power design strategies (UPF knowledge beneficial) and high-frequency design considerations.

Personal Traits

• Self-motivated and responsible, able to operate independently with minimal supervision.
• Strong analytical mindset and keen attention to detail in debugging complex timing issues.
• Excellent communication skills promoting effective cross-team collaboration with design, physical design, and verification teams.
• Enthusiastic about continuous learning, process improvement, and sharing expertise with teammates.

Team Environment

You will be part of a dynamic group of backend and STA engineers dedicated to delivering reliable and efficient timing and power closure solutions on advanced silicon projects. The team emphasizes technical excellence, cooperation, and ongoing enhancement aligned with customer success.

Compensation and Benefits

A comprehensive suite of health, wellness, and financial benefits will be provided. Compensation specifics will be communicated during the recruitment process.