Senior Staff ASIC Design Verification Engineer

About Synopsys

Synopsys leads the engineering sector by providing comprehensive solutions from silicon to systems, enabling rapid innovation in AI-driven products. Their offerings include cutting-edge silicon design, IP, simulation, analysis solutions, and design services, collaborating closely with diverse industries to enhance R&D and spark future innovations.

Role Summary

We are looking for an experienced and motivated ASIC Digital Verification Engineer who is passionate about technological advancement and tackling challenging problems. The ideal candidate has solid expertise in digital design and verification, proficient in validating complex ASIC designs using modern methodologies such as System Verilog and UVM to ensure thorough quality outcomes.

This role thrives in fast-paced collaborative settings, requiring a proactive, self-directed approach. The engineer will be adept at resolving intricate testbench and design issues, handling multiple priorities, and actively contributing technical insights across teams. The position values continuous learning, knowledge exchange, and the chance to influence cutting-edge product development.

Key Responsibilities

• Design and implement verification strategies for sophisticated ASIC designs, especially focusing on next-generation High Bandwidth Memory (HBM) products.
• Create and maintain comprehensive test cases using System Verilog and UVM frameworks.
• Diagnose and troubleshoot complicated testbench and design challenges while collaborating with design and mixed-signal teams to resolve verification flow issues.
• Leverage scripting languages such as Python or Perl to automate verification workflows for enhanced efficiency and coverage.
• Participate actively in design, architecture, and code reviews; document verification procedures and outcomes; and promote best practices to foster team learning and improve processes.

Impact of Your Work

• Accelerate the creation of high-performance and dependable HBM solutions tailored for next-gen computing and AI applications.
• Ensure robust silicon quality by meticulous verification planning, debugging, and execution.
• Enhance engineering productivity through advancement of verification methodologies, early problem detection, and ongoing process enhancements.
• Elevate team proficiency via collaboration, knowledge sharing, and significant technical contributions within the verification discipline.

Necessary Qualifications

• Bachelor’s or Master’s degree in Electrical Engineering with at least six years of experience in digital design and verification.
• Demonstrated proficiency in creating and managing testcases using System Verilog and UVM, along with strong capability in debugging complex testbench and design issues.
• Firm understanding of digital circuit design principles and experience automating workflows using Python or Perl scripting.
• Ability to operate both independently and collaboratively within a dynamic engineering environment.

Personal Attributes

• Highly self-driven, independent, and resourceful in addressing technical challenges.
• Effective communicator and cooperative in problem-solving with strong organizational capabilities.
• Flexibility, keen attention to detail, and dedication to ongoing learning and delivering quality results.
• Enthusiastic about innovation and fostering a culture of excellence.

Team Environment

You will join a seasoned mixed-signal design and verification group focused on developing the upcoming HBM product generations. This team comprises experienced digital and mixed-signal engineers dedicated to producing sophisticated mixed-signal designs from specification stage through prototype testing. The environment encourages collaboration, continuous training, and professional growth.

Benefits and Rewards

Synopsys offers a holistic package of health, wellness, and financial benefits tailored to employee needs, encompassing both monetary and non-monetary incentives. Detailed compensation information will be provided during the hiring procedures.