Senior R&D Engineer - Standard Cell Library Characterization

About Synopsys

Synopsys leads in engineering solutions that span silicon to systems, facilitating rapid innovation for AI-driven products. We provide top-tier silicon design, intellectual property, simulation, analysis solutions, and design services, collaborating closely with various industries to optimize R&D efficiency and empower future innovation.

Role Overview

As a seasoned professional in library characterization, you understand that the accuracy of a Liberty model hinges on thorough testing of corner cases and validated correlations. You recognize the impact of timing model mismatches on designers’ schedules and take this accountability seriously.

Your expertise lies in transitioning between SPICE simulations, Liberty file generation, and diagnosing discrepancies in CCS noise models across various process, voltage, and temperature (PVT) corners. When correlations falter between characterization and static timing analysis (STA), you actively investigate and identify the failures rather than merely reporting them.

You take full responsibility for the characterization flow: actively spotting issues, identifying trends in regression failures, and determining when models require refinement despite meeting specifications. At Synopsys, you’ll contribute to the creation of superior standard cell libraries used in advanced semiconductor designs, upholding uncompromising quality standards.

Key Responsibilities

• Perform comprehensive characterization and modeling of standard cell libraries for cutting-edge technology nodes, producing Liberty files encompassing NLDM, NLPM, CCS timing, CCS noise, ECSM, LVF, AOCV, POCV, spatial OCV, aging, and electromigration (EM) models.
• Manage characterization across diverse cell categories, including combinational, sequential, clock gating, synchronizers, retention, level shifters, power gating, always-on, filler, and decoupling cells.
• Diagnose and resolve correlation discrepancies between characterization outcomes, STA, and SPICE simulations by collaborating across tool flows to pinpoint root causes.
• Conduct quality assurance checks, regression analyses, and release validations to assure accuracy and quality of library deliverables prior to distribution.
• Lead initiatives to enhance methodologies and automate processes, accelerating characterization workflows and improving maintainability over multiple projects.
• Coordinate project schedules, oversee deliverables, and communicate progress effectively with cross-functional teams such as design, verification, and product engineering.
• Support library releases by validating models against design rule checks, performing sanity tests, and ensuring accurate, thorough documentation.

Impact and Contributions

• Facilitate precise timing closure in advanced node designs by delivering dependable Liberty models essential to designers and STA tools.
• Minimize correlation gaps between characterization and actual silicon behavior, enhancing predictability and reducing costly respins.
• Expedite library development by implementing automation and refining characterization flows adaptable to multiple technology nodes.
• Raise library quality through scrupulous QA, regression testing, and validation that detect issues before release.
• Enable successful tapeouts by ensuring libraries satisfy performance, power, and area specifications across all operational conditions.
• Drive methodology advancement by discovering gaps, proposing solutions, and executing enhancements beneficial to the entire characterization team.
• Help maintain Synopsys's leadership in library IP by delivering precise and robust models tailored to state-of-the-art semiconductor designs.

Required Qualifications

• Bachelor's or Master’s degree in Electronics, VLSI, Microelectronics, or a closely related technical discipline.
• More than two years of practical experience in standard cell library characterization and Liberty modeling.
• Deep understanding of Liberty file formats such as NLDM, CCS, ECSM, and advanced constructs including AOCV, POCV, and aging models.
• Experience with a wide variety of cell types including combinational, sequential, clock gating, level shifters, retention, and power management cells.
• Strong knowledge of SPICE simulation, timing analysis, and correlation techniques between characterization and STA tools.
• Proficiency in scripting languages like Python, Tcl, or Perl for developing automation, data processing, and flow management.
• Familiarity with industry-standard characterization tools and STA platforms is advantageous.

Personal Attributes

• Keen attention to detail in identifying inconsistencies such as timing arc anomalies or incorrect capacitance values within Liberty files and tracing them back to characterization settings.
• Proactive in addressing correlation problems by examining SPICE decks, waveform comparisons, and analyzing model divergences.
• Organized and capable of managing multiple parallel library releases while keeping track of validated, QA, or pending models.
• Effective communicator in explaining complex characterization challenges to technical leads or engineers with clarity and technical integrity.
• Assertive in defending thorough validation timelines to ensure high-quality model releases and avoid costly errors.
• Committed to integrating automation into routine tasks to replace repetitive manual work.

Team Environment

You will be part of Synopsys’s Library Characterization team responsible for characterization, validation, quality assurance, release supervision, and methodology support for advanced standard cell libraries across different technology nodes. The team closely collaborates with design, product engineering, and customer-facing groups.

Rewards and Benefits

Synopsys provides an extensive package of health, wellness, and financial benefits tailored to individual needs, comprising monetary and non-monetary rewards. Salary details and benefits will be discussed during the recruitment process.