Senior Engineer - EDA Flow and Logic Synthesis

About Synopsys

Synopsys pioneers innovations shaping modern life and connectivity, leading in chip design, verification, and IP integration that drive advanced silicon and software technology, central to pervasive intelligence such as autonomous vehicles and AI systems.

Role Overview

As a mid-end engineer within our HPC Controller IP team, you will bridge RTL design and physical implementation by creating flows, automation, and quality assurance to synthesize and release complex soft IP efficiently. You will provide physical-design teams with precise, constrained, and implementation-ready inputs.

Responsibilities

• Design, maintain, and operate mid-end flows including synthesis, DFT, SpyGlass static checks, formal equivalence verification, power analysis, and quality gates.
• Transform RTL outputs into clean, constrained inputs ready for physical design implementation.
• Develop and sustain Tcl-based automation, dashboards, and project infrastructure, leveraging AI to enhance productivity, debug efficiency, and output quality through techniques like flow log triage and QoR trend summarization.
• Investigate and resolve flow failures by root cause analysis and collaboration across design, verification, DFT, and implementation groups.
• Enhance documentation, handoff protocols, and reusable materials to maintain consistent execution across IP projects.

Impact

• Improved RTL to physical design handoffs with minimized implementation risks.
• Accelerated and scalable workflow execution through automation and AI-driven analytics.
• Earlier detection of synthesis, DFT, static analysis, formal, and power-related issues.
• Strengthened synergy along the RTL to implementation continuum.
• Delivery of robust, constrained, and fully checked soft IP releases.

Core Qualifications

• Practical understanding of ASIC design, verification, and mid-end development flows with at least 2 years of relevant hands-on experience or equivalent project background.
• Proven ability in synthesis, including problem analysis and resolution.
• Competence in Tcl scripting coupled with an automation-first approach.
• Familiarity with some of the following technologies: design-for-test (DFT), static checking tools such as SpyGlass, formal equivalence tools (e.g., Formality), or power analysis, with eagerness to expand expertise.
• Experience in leveraging AI tools for debugging acceleration, summarizing results, and enhancing scripts and workflows.
• Strong analytical abilities, problem-solving skills, clear communication, and thorough documentation.
• Bachelor's or Master's degree in Electrical or Computer Engineering, or comparable experience.

Preferred Qualifications

• Broad experience across mid-end domains including DFT, SpyGlass, Formality, and power analysis.
• Expertise in IP development methodologies, IP packaging, and delivery of reusable IP assets.
• Hands-on exposure to Synopsys tools like Fusion Compiler and VC SpyGlass.

Personal Attributes

• Initiative-driven, inquisitive, and adaptable to change.
• Team-oriented and ethical in collaboration.
• Flow-centric with awareness and utilization of AI, committed to quality.
• Persistent and goal-focused.

Team Environment

You will join a high-impact High-Performance-Compute team charged with delivering advanced IP products to market, coordinating across RTL design, verification, DFT, physical design, methodology, and infrastructure teams to boost mid-end readiness and ensure dependable downstream implementations.

Compensation and Benefits

Comprehensive health, wellness, and financial benefits are provided to support your needs. Specific salary and benefit details will be discussed during the recruitment process.