Senior Staff Analog Layout Engineer

About Synopsys

Synopsys is a frontrunner in providing engineering solutions spanning silicon to systems, enabling rapid innovation in AI-driven products. We specialize in market-leading silicon design, IP, simulation, analysis tools, and design services, collaborating closely with clients across diverse industries to enhance R&D productivity and spark tomorrow's technological breakthroughs.

Role Overview

We seek a seasoned professional who has dedicated nearly a decade to crafting analog layouts that excel beyond verification—they perform reliably in silicon under real-world operating conditions. Your expertise includes intricacies such as high-speed differential pairs, micro bump planning, and die-to-die interconnections. You understand that flawless Virtuoso layouts may still encounter package-level failures without foresight into return paths, skew, and substrate coupling.

You appreciate that floor planning is iterative, engaging constantly with circuit designers, packaging, and digital teams to refine layouts collaboratively. Certification setbacks close to tape out are met with composed troubleshooting to resolve and finalize designs.

Your experience spans chiplet architectures, 2.5D integration, and advanced packaging, with a profound understanding that UCIe represents a paradigm shift in analyzing die boundaries, signal integrity, and physical partitioning. At Synopsys, you would contribute to IP enabling chiplet communication, producing layouts integral to impactful products.

Key Responsibilities

• Create full-custom analog layouts for UCIe PHY components including transmitters, receivers, drivers, equalizers, DLLs, bias circuits, calibration engines, and regulators.
• Manage PHYTOP-level floor planning, micro bump architecture, bump planning, and channel routing while considering package co-design for 2.5D/3D integration.
• Implement precise high-speed differential routing focusing on length matching, skew management, shielding, symmetry, and signal integrity across die and package boundaries.
• Lead physical verification closure: DRC, LVS, ERC, antenna inspections, density regulations, LPE extraction, EM/IR analysis, and reliability signoff.
• Work conjointly with ASIC physical design teams to integrate analog layouts, generate LEF files, support place-and-route processes, and address integration challenges.
• Develop and refine layout methodologies, automation tools, and reusable design flows to boost team efficiency and consistency.
• Conduct technical design reviews, mentor junior layout engineers, resolve complex design integration issues, and spearhead tape out coordination with global teams.

Impact of Your Work

• Your layouts will empower UCIe die-to-die interfaces incorporated in emerging chiplet applications within the semiconductor sector.
• The floor plans and bump configurations you engineer will determine how analog PHY designs mesh with digital logic and packaging in advanced 2.5D/3D systems.
• Your contributions to signal integrity will be pivotal in ensuring that high-speed channels meet performance criteria in actual silicon implementations.
• Innovations in verification methods and automation you pioneer will accelerate tape out timelines and minimize redesign iterations for future PHY products.
• Your teamwork with packaging and digital integration units will troubleshoot and prevent integration obstacles that might otherwise hinder product quality and delivery.
• Your mentorship efforts will equip fellow engineers with lasting layout techniques and problem-solving skills.
• Through your input, Synopsys will maintain leadership in producing industry-defining UCIe IP, supporting the next wave of chiplet technology.

Required Qualifications

• Diploma or Bachelor's degree in Electrical, Electronics Engineering, or a related technical field.
• 8 to 15 years of practical experience in analog or mixed-signal custom IC layout design.
• Documented success designing UCIe PHY, high-speed SerDes, or die-to-die interface IP layouts with tape out achievements.
• In-depth knowledge of micro bump planning, bump map architectures, package-aware floor planning, and co-design for 2.5D/3D integration including interposers, RDL, and TSV technology.
• Expertise in high-speed differential routing, including precise length tuning, skew reduction, shielding methods, symmetry, and signal integrity focused layout practices.
• Experience resolving physical verification challenges (DRC, LVS, ERC, EM/IR, antenna rules, density, reliability) for advanced process nodes through tape out.
• Familiarity with analog layout integration into ASIC physical flows, LEF generation, and system-level validation is highly desirable.

Candidate Attributes

• Confidence in addressing floor planning with partial specifications, asking pertinent questions about power and signal paths, leading to viable layout strategies.
• Proactive evaluation of micro bump changes' impact on routing, return paths, and cross-talk beyond simple layout updates.
• Ability to diagnose and rectify subtle LVS mismatches under tight deadlines.
• Effective communication with circuit designers to balance EM limitations with performance and reliability in placement planning.
• Capability to manage multiple concurrent layout blocks, track verification outcomes, and coordinate integrations while adhering to tape out schedules.
• Clear documentation skills enabling seamless handoffs across global teams and time zones.

Additional Information

The recruiting team will provide detailed insights on team composition, mission, salary range, and benefits during the recruitment process. The company offers a wide array of health, wellness, and financial benefits, covering both monetary and non-monetary compensation to support employee needs.