Analog Mixed-Signal Layout Manager

About Synopsys

Synopsys leads in engineering solutions spanning silicon to systems, empowering customers to quickly innovate AI-driven products. They provide top silicon design, IP, simulation, analysis software, and services, partnering broadly with clients across industries to enhance R&D efficiency and innovation.

Role Overview

We seek a seasoned expert in analog and mixed-signal layout with leadership skills to enhance execution through AI-powered productivity, automation, and methodology advancement. This role involves working on SerDes analog layout in cutting-edge nodes, driving complex program execution, and modernizing layout engineering practices.

Key Duties

• Lead successful delivery of SerDes analog layout projects in advanced semiconductor process nodes, ensuring quality, timely completion, and managing technical risks.
• Enhance layout methodologies focusing on floorplanning, matching, shielding, ESD integration, and physical verification processes.
• Collaborate routinely with design, ESD, reliability, CAD teams, and project managers to align layout work with design goals and milestones.
• Implement automation, scripting, dashboards, and AI-assisted workflows to boost consistency, reduce manual tasks, and scale engineering output.
• Provide mentorship on advanced layout methods, design compromises, and execution standards, uplifting team expertise.
• Influence resource allocation, planning, tool use, and process improvements through cross-functional leadership.
• Possibly lead a team of layout engineers or act as technical lead setting best practices and methodology standards across projects.

Impact Expectations

• Produce high-speed analog layouts meeting performance, reliability, and manufacturability standards for advanced nodes.
• Minimize layout cycle times and revisions by deploying automation and clearer workflow integrations.
• Promote collaborative integration between design, layout, ESD, and CAD teams for smooth execution.
• Create reusable methodologies and automation solutions applicable across different programs and locations.
• Elevate team capabilities through effective mentorship, technical guidance, and clear execution norms.
• Contribute to the delivery of leading-edge SerDes IP for next-generation semiconductor products.

Candidate Qualifications

• Bachelor’s or Master’s degree in Electrical Engineering, Electronics, or similar disciplines.
• Minimum 12 years in analog or custom layout focusing on high-speed analog and mixed-signal design implementations.
• Extensive experience with layout implementation and methodology in advanced semiconductor nodes.
• Proven collaboration with multidisciplinary teams including design, ESD, CAD, and program management to meet complex layout deadlines.
• Track record in advancing engineering productivity via automation, methodology enhancements, dashboard development, or workflow streamlining.
• Leadership qualities including team management, execution planning, mentoring, technical problem solving, and cross-team methodology advocacy; interest or experience applying AI and automation in layout tasks is a plus.

Additional Information

You will be part of a team whose structure and mission will be detailed in the interview phase. Comprehensive health, wellness, and financial benefits are provided, alongside competitive total rewards including monetary and non-monetary components. Salary details will be shared during hiring discussions.