FPGA Lead

About the Role

We are looking for a talented RTL Design Engineer with deep expertise in AMD-Xilinx FPGA architecture to develop Register-Transfer Level Intellectual Property focused on video connectivity subsystems. This position involves diverse tasks including defining projects, designing RTL, and implementation activities. The engineer will contribute to architecture, documentation, and implementation of low latency video connectivity systems, alongside RTL coding of assigned blocks. The role also encompasses various frontend methodology flows such as resource optimization and managing clock and reset domain crossings.

Qualifications

• Demonstrated experience working with video domain or digital IPs.
• Proven expertise implementing one or more IP-level protocols like MIPI CSI, MIPI DSI, DisplayPort, HDMI, or SDI.
• Practical knowledge of AMD/Xilinx FPGA devices and Vivado toolchain.
• Hands-on skills in architecture, micro-architecture, and detailed design from functional specifications.
• Proficiency in synthesizable Verilog or SystemVerilog RTL coding for FPGA designs.
• Experience with linting, clock domain crossing (CDC), synthesis, static timing analysis, and formal verification processes.
• Working familiarity with scripting languages such as TCL, Perl, and Python is advantageous.
• Knowledge of SERDES architecture is considered a plus.
• A strong willingness to continuously learn and adapt to new technologies.
• Excellent communication and presentation capabilities.
• Comfort collaborating closely with cross-functional teams across multiple time zones.