Synthesis and STA Lead

Position Overview

We seek a seasoned Synthesis and Static Timing Analysis (STA) Lead to oversee timing closure and synthesis tasks for advanced semiconductor designs. This role involves delivering high-quality STA results for complex, high-frequency circuits, ensuring optimal performance across various operational scenarios.

Key Responsibilities

• Lead timing closure efforts providing sign-off grade static timing analysis across multifaceted designs operating under multiple modes and conditions.
• Translate technical proficiency into tangible client benefits including quicker project turnaround, enhanced quality of results, and balanced power-performance-area trade-offs.
• Develop and validate timing constraints to ensure design robustness and facilitate smooth integration into client development flows.
• Manage synthesis workflows leveraging Fusion Compiler and Design Compiler tools, achieving targets aligned with customer expectations on timing, area, and power consumption.
• Collaborate extensively with RTL, physical design, and test teams to proactively tackle design challenges and maintain timely delivery milestones.
• Integrate AI-driven reinforcement learning methodologies (such as DSO.ai) to expedite design space exploration and minimize turnaround time.
• Implement and verify Unified Power Format (UPF) based low-power design strategies that fulfill energy efficiency requirements.
• Ensure functional accuracy through formal verification processes and Engineering Change Order (ECO) generation to support reliable customer tape-outs.

Candidate Qualifications

• Bachelor’s degree in Electrical Engineering or related fields from recognized institutions.
• 8 to 10 years of experience in semiconductor design within prominent organizations.
• Specialized knowledge in static timing analysis, synthesis, constraints definition, and low-power validation.
• Proficiency with tools including PrimeTime, Fusion Compiler, Design Compiler, Formality, ICC2, Conformal, and VCLP.
• Strong scripting and hardware description skills with TCL, Python, Perl, and Verilog.
• In-depth understanding of challenges associated with advanced semiconductor nodes such as crosstalk, on-chip variation (OCV, AOCV, POCV), and complex clock tree architectures.