ASIC/SoC Design Engineer
Hyderabad, Telangana, India · Full Time
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- Experience
- 7+ yrs
- Salary
- —
- Openings
- 1
- Posted
- 12 seconds ago
- Work mode
- In office
- Education
- B.Tech / B.E.
- Eligibility
- Individuals with B.Tech or B.E. degrees in any discipline are invited to apply.
- Resume
- Required to apply
Where you'll work
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Job description
About the Role
This position offers a chance to join a leading company specializing in Smart Edge SoCs for network and system control, security management systems, and Industrial Internet of Things (IIoT) applications. The role requires strong knowledge in logic design and computer architecture. As an ASIC/SoC Design Engineer, you will engage in all phases of the SoC design lifecycle and collaborate closely with multiple cross-functional teams including Architecture, Verification, Physical Design, and Software.
Key Responsibilities
- Contribute to the design and implementation of SoCs.
- Perform micro-architecture design, RTL coding, synthesis, timing closure, and document RTL modules.
- Optimize performance, bandwidth, and power at both top-level and block-level.
- Work alongside FPGA engineers for early-stage prototyping.
- Support development of test programs, chip validation, and oversee chip lifecycle until it reaches production readiness.
- Collaborate with firmware, software, design verification, FPGA, design-for-test, SoC integration, and backend teams throughout various steps of ASIC development.
Required Qualifications
- Minimum 7 years of experience in RTL logic design, verification, synthesis, and timing optimization.
- Proficient in authoring clear and implementable micro-architecture specifications.
- Strong expertise in efficient RTL coding in Verilog and SoC integration techniques.
- Good understanding of assertions, coverage analysis, RTL synthesis, and timing closure processes.
- Experience working with interface protocols such as PCIe, USB, Ethernet, DDR3/4, LPDDR, I2C/I3C, SPI, SD/SDIO/eMMC, UART, etc.
- Familiarity with FPGA-based emulation platforms (e.g., HAPS, Veloce) for design bring-up and debugging.
- Competency in scripting languages like Perl and Python.
- Must have participated in at least one tapeout cycle.
Preferred Skills
- Experience with silicon bring-up and debugging.
- Knowledge of repository management tools such as Bitbucket and Jenkins.
- Familiarity with bug tracking systems like JIRA.
Eligibility and Education
Candidates holding a B.Tech or B.E. degree in any specialization are eligible to apply.
Minimum education
Bachelor's Degree