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ASIC Design Lead

G.t.d Technologies

Hyderabad, Telangana, India · Full Time

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Experience
8–12 yrs
Salary
—
Openings
1
Posted
14 hours ago
Work mode
In office
Education
B.Tech / B.E.
Eligibility
Candidates must have completed B.Tech or B.E. in any specialization.
Resume
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Where you'll work

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Job description

Overview

We are looking for a seasoned ASIC Design Lead to join our semiconductor manufacturing organization based in Hyderabad. The role involves leading microarchitecture development, module design, digital implementation, and integration of complex systems on chip (SoCs) and microcontrollers.

Key Responsibilities

  • Lead microarchitecture design, develop modules, and run simulations.
  • Execute digital design tasks including RTL coding, linting, CDC troubleshooting, and synthesis process.
  • Create design constraints, and collaborate to resolve functional and DFT testing challenges.
  • Generate synthesis and place & route constraints, especially related to clock tree specifications.
  • Manage scan insertion and pattern generation activities.
  • Support cross-functional teams including IP, verification, firmware, and software for efficient resolution of block design and implementation issues.

Required Qualifications and Skills

  • Bachelor's degree in Electrical or Electronics Engineering is mandatory; Master's preferred.
  • 8 to 12 years of industrial experience focused on digital or mixed-signal IC design.
  • Strong digital design expertise including Verilog coding, register file design, serial interface development, interconnect fabric architectures, state machine design, clock domain crossing, scan and self-test techniques.
  • Proficient in synthesis, linting, static timing analysis (STA).
  • Experienced in automation scripting and smooth design flow implementation.
  • Verification skills, including knowledge of SystemVerilog.
  • Competency in low power design practices, power intent specification, and validation methodologies.
  • Familiarity with system-level knowledge such as battery management and RISC-V based subsystems and SoCs.
  • Working knowledge of industry-standard EDA tools including Cadence and Synopsys.
  • Understanding of tools, flows, and methodologies (TFM) for simulation, lint, CDC/RDC, and power-intent checks using UPF.
  • Ability to collaborate efficiently within a team environment while working with minimal supervision.

Eligibility

Applicants must hold a B.Tech or B.E. degree in any specialization.

Minimum education

Bachelor's Degree

Industry

Semiconductors

Tools & software

How they work

Teamwork & Collaboration Independence

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