Senior Staff Engineer - Logic Design and Verification

Company Overview

Synopsys leads in providing engineering solutions from silicon to systems, enabling customers to rapidly develop AI-driven products. Their portfolio includes premier silicon design tools, IP cores, simulation and analysis software, and design services, partnering closely across diverse industries to enhance R&D productivity and spark future innovations.

Role Overview

We are seeking a seasoned professional with over ten years of experience in verification environments focused beyond mere coverage metrics, capable of designing complete UVM environments and crafting stress sequences for advanced interface IP in silicon chips.

Key Responsibilities

• Work collaboratively with design teams to establish verification objectives and translate specifications into comprehensive test plans that validate functionality, edge conditions, and performance.
• Design and develop full UVM testbench environments, including reusable agents, scoreboards, and verification components tailored for interface IP designs.
• Create SystemVerilog test sequences utilizing constrained random stimulus to rigorously test designs and reveal hard-to-find corner cases before silicon fabrication.
• Develop and deploy SystemVerilog Assertions for functional verification in simulation and formal verification environments.
• Generate and assess functional and code coverage metrics, pinpoint shortcomings, and drive efforts to achieve full coverage.
• Lead a team of verification engineers by mentoring in UVM methodologies, debugging strategies, and testbench architecture excellence.

Impact and Outcomes

• Successfully deliver thoroughly validated interface IP meeting tape-out schedules and stringent quality standards, enabling customers to produce high-performance silicon.
• Improve verification efficiency and defect detection through robust, reusable verification IP and optimized methodologies.
• Set verification standards and best practices that support scalability across various projects and teams.
• Boost team effectiveness by transferring expertise on UVM, formal verification, and debugging techniques.
• Identify critical design flaws early, minimizing expensive rework and accelerating market readiness.
• Create verification environments that serve as reference models for future development.

Required Qualifications

• Bachelor’s or Master’s degree in Computer Engineering, Electrical Engineering, or Communication Engineering.
• More than 8 years of ASIC design verification experience, emphasizing UVM-based functional verification.
• Advanced proficiency in SystemVerilog, including sophisticated testbench creation, constrained random stimulus, and coverage-driven verification.
• Proven skills in implementing SystemVerilog Assertions for both simulation and formal verification workflows.
• Strong programming capabilities in at least two of the following: C, SystemVerilog, TCL, Perl, or Python.
• Experience with PCI Express and CXL protocols is desirable.
• Working knowledge of interface IP verification, formal verification tools such as Jasper or VC Formal, and AI-assisted coding tools like Cursor or GitHub Copilot will be advantageous.

Personal Attributes

• An exceptional ability to detect verification weaknesses in design reviews and convincingly communicate their importance to prioritize remediation.
• Meticulous code reviewing skills that provide clear, constructive feedback fostering improvement.
• Proactive mindset capable of progressing projects with incomplete data by asking pertinent questions and making informed decisions.
• Natural aptitude for teaching complex topics like UVM factory overrides and coverage bin construction in an accessible manner for less experienced engineers.

Team and Additional Information

Further details about the team structure and goals will be shared during the interview process.

Compensation and Benefits

The company offers an extensive suite of health, wellness, and financial benefits designed to meet diverse needs. Both monetary compensation and non-financial rewards form part of the overall package; specifics will be discussed during recruitment.