Senior Design Verification Engineer

Position Overview

We are looking for a highly experienced Senior Design Verification Engineer to lead the verification efforts on cutting-edge PCIe and CXL Controller and Subsystem IPs. This position involves designing sophisticated verification environments, creating thorough test plans, and validating functional correctness for complex, high-speed interconnect technologies. The role demands deep expertise in protocols, mastery of UVM methodology, and strong troubleshooting capabilities within a collaborative engineering team.

Key Responsibilities

• Develop, architect, and maintain elaborate constrained-random testbenches from the ground up using SystemVerilog and UVM frameworks.
• Manage the complete verification process lifecycle for high-performance PCIe and CXL controller IPs and subsystems.
• Create detailed verification plans aligned with functional specifications; perform testing and ensure closure of functional and code coverage goals.
• Perform advanced debugging of design, testbench, and protocol-related issues efficiently using industry-standard tools and waveform viewers.
• Collaborate closely with architecture, design, and firmware teams to troubleshoot hardware bugs and clarify specification details.

Required Skills and Qualifications

• Profound, practical expertise with PCIe (Gen 4/5/6) and CXL (1.1/2.0/3.0+) protocols, including sub-protocols like cxl.io, cxl.cache, and cxl.mem.
• Demonstrated strong skills in UVM testbench development, building scalable and reusable verification environments.
• Advanced knowledge of SystemVerilog, SystemVerilog Assertions (SVA), and functional coverage techniques.
• Excellent analytical ability and problem-solving skills, capable of debugging complex issues under tight timelines.
• Strong adaptability to grasp complex architectural concepts quickly, self-driven attitude, and effective collaboration across global teams.

Preferred Qualifications

• Experience with formal verification methodologies or gate-level simulation (GLS).
• Familiarity with hardware description languages like Verilog and VHDL to aid in design code reviews.
• Knowledge of scripting languages such as Python, Perl, or Tcl for automation of regression testing.

Eligibility

Applicants should hold a graduate degree.