Senior Layout Engineer - DRAM Engineering

About the Company

Micron Technology, a global leader specializing in advanced memory and semiconductor technologies for over 40 years, drives innovations that transform information use to enrich lives worldwide. The company delivers leading solutions in DRAM, NAND, and NOR memory products, fueling advances in AI, 5G, and data economy.

Role Overview

We are seeking a Senior Layout Engineer to join Micron's DRAM Engineering Group in Hyderabad, India. This role involves collaboration with international teams to deliver high-quality full-chip and block-level layouts across multiple projects, ensuring adherence to timelines and technical excellence.

Key Responsibilities

• Lead design and development of complete chip layouts in analog, digital, memory, and ESD domains, making technical decisions affecting the full chip including Electromigration and IR drop considerations.
• Establish and enforce layout guidelines concerning technical quality for successful full-chip layout execution.
• Conduct layout verification such as LVS, DRC, and antenna checks, along with thorough quality assurance and documentation.
• Ensure on-schedule delivery of layouts with high-quality standards.
• Demonstrate leadership in project planning, time and resource estimation, scheduling, task delegation, and execution within a multi-project environment.
• Partner with design, verification, CAD, DTCO, PI, and other cross-functional teams to define and realize layout solutions.
• Develop methodologies, layout standards, best practices, and promote automation and scripting to enhance productivity.
• Mentor junior engineers on sub-block layouts and review their outputs.
• Contribute to ongoing innovation through papers, seminars, disclosures, and share expertise across the layout organization.
• Recruit, build, and manage proficient teams aligned with global layout standards.
• Communicate effectively with international engineering teams across the US, Japan, and Germany to align project goals and success.
• Utilize AI tools to author precise technical prompts for design and verification use cases and critically assess AI outputs before integrating results into design decisions.

Mandatory Qualifications and Experience

• Minimum of 15 years experience in analog and custom layout design using advanced CMOS processes.
• Proficiency in Cadence VLE/VXL and Calibre DRC/LVS tools is essential.
• Hands-on experience with critical analog blocks including temperature sensors, PLLs, ADCs, DACs, LDOs, Bandgaps, reference generators, charge pumps, current mirrors, comparators, and differential amplifiers.
• Experience working with various memories such as DRAM, SRAM, CAM, and OTP.
• Strong understanding of analog layout principles including device matching, electromigration, latch-up, coupling and cross-talk, IR drop, and parasitic devices.
• Ability to comprehend circuit impacts such as speed, capacitance, power consumption, and area due to layout.
• Capability to translate design constraints into high-quality layout implementations.
• Proven leadership in managing multiple projects and tape-outs.
• Experience with layout verification problem solving.
• Working knowledge of scripting and automation techniques.
• Excellent verbal and written communication skills.
• Educational background: B.E. or M.Tech in Electronics or VLSI Engineering.

Additional Information

Micron ensures equal employment opportunities without discrimination based on race, color, religion, gender, sexual orientation, gender identity, nationality, veteran status, or disability. The company prohibits child labor and complies with all relevant labor laws and industry standards. Candidates are warned against fraudulent job offers and are advised to verify authenticity through official channels. Use of AI tools for application enhancement is encouraged, provided all information is accurate and truthful.

Reasonable accommodations can be requested during the application process by contacting the designated support.