Memory Design Automation Engineer – Memory Compiler (2027 Campus Hire)

Job Overview

We are seeking a Memory Design Automation Engineer specialized in SRAM compiler development at advanced technology nodes. This role involves delivering high-quality design kits and collaborating seamlessly with SRAM design and layout teams.

Key Responsibilities

• Lead the design and delivery of SRAM compilers optimized for cutting-edge technology nodes.
• Work closely with SRAM design and layout teams to ensure the highest quality design kit output.
• Perform data analysis and develop platforms for managing large-scale memory usage data.
• Handle physical verification tasks including DRC, ERC, LVS, Antenna checks, and PERC on the SRAM compiler.
• Conduct spice simulations focusing on timing, power consumption, and noise parameters of SRAM compilers.
• Carry out quality assurance checks and contribute to the development improvements of SRAM compilers.

Qualifications and Requirements

• Possess a Bachelor's or Master's degree in Electrical/Electronic Engineering, Computer Engineering, or Computer Science.
• Demonstrate strong multitasking abilities and a proactive, self-driven approach to meet demanding timelines.
• Proficient programming skills in Perl, Shell, Python, and C/C++ languages.
• Familiarity with AI and machine learning algorithms and infrastructure is a plus.
• Exhibit excellent interpersonal skills suitable for collaborating within a multicultural team environment.
• Knowledge of high-performance, low-power SRAM/ROM and VLSI design is advantageous.
• Experience with Electronic Design Automation (EDA) tools will be beneficial.