Senior Verification Engineer

Job Overview

We are looking for a Senior Verification Engineer to design and implement verification plans based on design specifications. The ideal candidate will innovate to enhance design and verification flows, and develop IPCRV environments. A deep understanding of complex specifications is required, and familiarity with 3GPP standards or Serdes technology will be advantageous.

Qualifications

• Master's or Bachelor's degree in Electronics or Communication Engineering.
• Between 4 to 10 years of experience in digital hardware verification.

Responsibilities

• Create and execute verification plans derived from design documentation.
• Innovate and propose new methods to optimize design and verification processes.
• Develop and maintain IPCRV verification environments.
• Interpret and work with complex technical specifications.

Requirements

• Strong foundation in digital logic design.
• Hands-on experience with hardware verification languages such as SystemVerilog (SV).
• Proficient with industry-standard verification methodologies, especially Universal Verification Methodology (UVM).
• Excellent analytical, logical reasoning, and problem-solving capabilities.
• Effective communication skills for collaborating across multi-site teams.
• Strong teamwork ethic, high accountability, and dedication to hard work.
• Knowledge of Digital Signal Processing and Communication Engineering fundamentals is a plus.