Engineer/Staff Engineer – Multi-Dies Physical Verification Engineer

About the Role

Become a part of MediaTek's Chip Physical Verification team and contribute to creating innovative technologies for products that impact millions daily. This position focuses on defining and implementing physical sign-off processes and solutions tailored for SoC and Multi-Dies (3D IC) designs, ensuring flawless product tape-out. The role involves working with advanced semiconductor process nodes to ensure cutting-edge product success.

Key Responsibilities

• Manage Multi-Dies Physical Verification Sign-off covering 3D_Stack, 3D_PERC, and 3D_ANT for product tape-out.
• Collaborate closely with the Package Design Team to address integration challenges related to Multi-Dies.
• Coordinate with the ESD Team to execute the 3D_PERC process flow.
• Work jointly with the Chip Physical Verification Team on issues related to active dies, including DRC, LVS, ANT, ERC, and ESD checks.
• Develop automation tools to enhance tape-out process efficiency.
• Provide comprehensive reports on Physical Verification issues encountered during tape-out.

Required Qualifications and Expertise

• Bachelor's or Master's degree in Electrical/Electronics Engineering or Computer Science.
• Working knowledge of 3D IC design technologies such as CoWoS, SoIC, EMIB.
• Understanding of the complete IC design flow from front-end to back-end processes.
• Experience with Calibre tools is highly desirable.
• Strong scripting skills in languages such as Python, Tcl, Perl, or C-shell.
• Proficiency with UNIX/Linux operating systems.
• Excellent communication abilities coupled with strong analytical and problem-solving skills.

Location

This role is based at One North, Singapore.