SoC STA/Timing Engineer - Staff Level

Company Overview

Qualcomm India Private Limited is seeking experienced professionals for its Engineering Group specializing in Hardware Engineering to join their team in Bengaluru, Karnataka, India.

Role Summary

This role requires deep expertise in Static Timing Analysis (STA) for SoC and SubSystem designs, with experience handling complex multi-mode and multi-voltage domain environments.

Key Responsibilities

• Conduct STA setup, convergence processes, comprehensive reviews, and final signoff for multiple voltage domain designs within SoC and SubSystem projects.
• Perform timing analysis and debugging exercises across various Process, Voltage, and Temperature (PVT) conditions utilizing tools such as PrimeTime and Tempus.
• Optimize Static Timing Analysis workflows by correlating Spice simulation results with STA outcomes.
• Develop and evaluate timing methodologies and tools across different technology nodes, automating STA and physical design flows with scripting languages including TCL, Perl, and Python.
• Collaborate extensively with cross-functional teams including design, DFT, synthesis, technology, CAD, and physical implementation groups.
• Apply knowledge of low-power design techniques such as clock gating, power gating, and managing multi-voltage domains in timing analysis.
• Manage timing Engineering Change Order (ECO) flows using tools like DMSA, Tweaker, PrimeClosure and conduct logical equivalence checks transitioning from RTL to netlist.

Required Competencies

• Proficient understanding of STA fundamentals, including Advanced On-Chip Variation (AOCV), Process On-Chip Variation (POCV), Clock Tree Synthesis (CTS), and establishing timing constraints.
• Hands-on experience with STA software tools such as Synopsys PrimeTime and Cadence Tempus.
• Familiarity with ASIC back-end tool flows, specifically ICC2 and Innovus.
• Understanding of signal integrity issues including cross-talk noise and parasitic extraction impacts.
• Expertise in scripting for automation using TCL, Perl, and Python.
• Experienced in mentoring and guiding junior engineers on timing methodologies and flow optimizations.
• Knowledgeable in Spice-based simulations such as HSpice, FineSim, and Monte Carlo analysis.

Preferred Experience

• Proven ability to drive timing convergence efforts at both chip-level and hard-macro levels.
• Exposure to the full RTL-to-GDSII implementation flow.
• Strong written and verbal communication skills to facilitate effective collaboration across teams.

Educational Qualifications

• Bachelor's degree in Computer Science, Electrical/Electronics Engineering, or a related field with at least 4 years of relevant hardware engineering experience.
• OR Master's degree in the aforesaid fields with a minimum of 3 years of related experience.
• OR PhD in the related fields with at least 2 years of practical hardware engineering experience.

Additional Information

Qualcomm is an equal opportunity employer committed to accessibility and inclusivity. Individuals with disabilities requiring accommodations during the hiring process can contact the company directly via designated email or phone. Qualcomm enforces rigorous adherence to confidentiality and security policies protecting proprietary company information. Recruiting agencies are not authorized to submit applications on behalf of candidates; unsolicited resumes from agencies are not accepted.