Principal NPU Synthesis Engineer

About the Role

We are looking for a driven Principal Synthesis Engineer to join our Neural Processing Unit (NPU) design team. In this role, you will lead the RTL-to-GDS synthesis and timing closure processes for cutting-edge AI/ML accelerator chips integrated into upcoming system-on-chips (SoCs). You will collaborate across several teams including Architecture, RTL Design, Static Timing Analysis (STA), Design for Test (DFT), and Physical Design to produce power-efficient, high-quality silicon on advanced technology nodes.

Key Responsibilities

• Manage RTL-to-gate synthesis and timing closure for NPU intellectual properties and subsystems.
• Create and maintain synthesis flows, define constraints, and automate complex hierarchical designs.
• Lead pre-layout and post-layout timing closure effort covering various operational modes and manufacturing corners.
• Optimize for performance, power, and area targets through physical-aware synthesis techniques.
• Develop, verify, and maintain timing constraints (SDC files), clock architecture, false paths, and multicycle path specifications.
• Coordinate with RTL, DFT, STA, and physical design teams to troubleshoot Quality of Results (QoR), timing, power, and convergence challenges.
• Conduct quality validation such as Logical Equivalence Checking (LEC), Clock Domain Crossing (CDC) checks, linting, and low-power verifications.
• Enhance synthesis quality by scripting improvements and refining flow processes.
• Support tapeout activities and continuously improve synthesis methodologies.

Required Qualifications and Skills

• Bachelor's or Master's degree in Electrical/Electronics Engineering, Computer Engineering, or a related discipline.
• Deep understanding of ASIC design processes from RTL through to GDSII.
• Hands-on experience with RTL synthesis, timing closure, and constraint definition.
• Proficiency in Synopsys Design Compiler/Fusion Compiler or Cadence Genus synthesis tools.
• Expertise in timing analysis using PrimeTime.
• Experience implementing low-power design techniques and UPF flows.
• Strong knowledge of clock architectures, timing constraints, and timing sign-off processes.
• Skillful in scripting with TCL, Python, or Perl for automation and analysis.
• Strong problem-solving, debugging capabilities, and effectiveness in cross-disciplinary team collaboration.

Preferred Experience

• Background with AI/ML accelerators, NPU, DSP, GPU, CPU, or other high-performance compute architectures.
• Experience working at advanced semiconductor technology nodes (5nm, 4nm, 3nm, and below).
• Familiarity with physical-aware synthesis and hierarchical design practices.
• Knowledgeable in quality verification flows including LEC, CDC, lint, power analysis, and low-power verification.
• Demonstrated history of successful SoC or intellectual property tapeouts.

Experience Levels

• Senior Engineer: 3-5 years
• Lead Engineer: 5-8 years
• Staff Engineer: 8-12 years
• Senior Staff Engineer: 12-18 years
• Principal Engineer: 18+ years

Additional Information

Qualcomm is an equal opportunity employer committed to providing reasonable accommodation to applicants with disabilities during the hiring process. Contact for accommodations is available via email or phone with dedicated support. Qualcomm expects all employees to abide by company policies including security and confidentiality requirements. Staffing agencies are not authorized to submit resumes or applications through this site.