Senior Staff NPU AI/Processor Synthesis Engineer

About the Role

Qualcomm India Private Limited is searching for a driven Synthesis Engineer or Lead to become part of their Neural Processing Unit (NPU) design team. This position involves managing the process from RTL to GDS synthesis and timing closure for cutting-edge AI/ML accelerators designed for forthcoming system-on-chips (SoCs). The role requires collaborating closely with teams specializing in Architecture, RTL Design, Static Timing Analysis (STA), Design for Test (DFT), and Physical Design to deliver high-quality and power-efficient silicon on advanced semiconductor technology nodes.

Key Responsibilities

• Lead the RTL-to-gate synthesis and timing closure efforts for NPU IPs and associated subsystems.
• Develop and upkeep synthesis workflows, constraints, and automation for complex hierarchical hardware designs.
• Oversee timing closure before and after layout, considering multiple modes and manufacturing process variations.
• Optimize performance, power, and area (PPA) of designs using physical-aware synthesis techniques.
• Create, verify, and maintain detailed timing constraints such as SDC files, clock definitions, false paths, and multi-cycle timing paths.
• Work synergistically with RTL, DFT, STA, and Physical Design teams to troubleshoot and resolve quality of results (QoR), timing, power, and convergence challenges.
• Conduct quality assurance checks including Logic Equivalence Checking (LEC), Clock Domain Crossing (CDC) verification, linting, and low-power verification.
• Analyze synthesis quality metrics and enhance flows via scripting and automation improvements.
• Support tapeout procedures and continuously refine synthesis methodologies.

Required Qualifications

• Bachelor's or Master's degree in Electrical Engineering, Electronics, Computer Engineering, or a closely related discipline.
• Comprehensive knowledge of ASIC design flows spanning RTL to GDS phases.
• Hands-on experience with RTL synthesis, timing closure processes, and developing constraints.
• Expertise in Synopsys Design Compiler, Fusion Compiler, or Cadence Genus tools.
• Strong proficiency in timing analysis using PrimeTime software.
• Experience applying low-power design strategies, including UPF-based flows.
• Solid understanding of clock architecture, timing constraints, and timing signoff criteria.
• Proficiency with scripting languages such as TCL, Python, or Perl.
• Excellent abilities in debugging, problem resolution, and cross-department collaboration.

Preferred Qualifications

• Prior work on AI/ML accelerators, including NPU, DSP, GPU, CPU, or other high-performance computing architectures.
• Familiarity with advanced semiconductor technology nodes such as 5nm, 4nm, 3nm and beyond.
• Experience with physical-aware synthesis techniques and hierarchical hardware design methodologies.
• Knowledgeable in LEC, CDC, linting, power analysis, and low-power verification flows.
• A proven history of successful tapeouts of SoCs or IP blocks.

Experience Requirements Based on Level

• Senior Engineer: 3-5 years of applicable experience.
• Lead Engineer: 5-8 years of applicable experience.
• Staff Engineer: 8-12 years of applicable experience.
• Senior Staff Engineer: 12-18 years of applicable experience.
• Principal Engineer: Over 18 years of applicable experience.

Additional Information

Qualcomm is an equal opportunity employer dedicated to making the workplace accessible for individuals with disabilities and offering reasonable accommodations during hiring processes. Communication regarding disability accommodations can be made via Qualcomm's designated email and toll-free contact. All employees must follow company policies, including those relating to confidentiality and security of proprietary information.

Recruitment agencies are not authorized to submit candidate information via Qualcomm's career site or other channels; unsolicited resumes will not be considered and related fees are not warranted.