Senior/Staff Engineer, Technical Manager - Design Verification

Job Overview

We are seeking an experienced Senior or Staff Engineer to lead the design verification efforts as a Technical Manager. The role involves developing and reviewing comprehensive test plans along with creating verification environments and testbenches spanning Module, IP, and SoC levels. You will also be responsible for building verification IPs and reference models, executing tests based on coverage-driven methodologies with randomization, and ensuring closure of both functional and code coverage metrics.

Key Responsibilities

• Create and review test plans tailored to various design stages.
• Design verification environments and testbenches at Module, IP, and SoC levels.
• Develop verification IP and reference models to support test scenarios.
• Implement tests using randomization techniques aligned with coverage-driven verification methodologies.
• Drive functional and code coverage closure to meet verification goals.
• Perform hands-on coding and debugging using UVM, SystemVerilog, Verilog, and SystemC.
• Conduct low power verification and formal verification efforts.

Qualifications and Skills

• Bachelor's or Master's degree in Electrical and Electronic Engineering, Computer Engineering, or IC Design.
• 4 to 10 years of experience in verification, particularly in IC/ASIC SOC design verification.
• Expertise in verifying protocols and interfaces including Ethernet, PCIe, DDR, USB, and ARM CPU.
• Strong skills in SystemVerilog and UVM methodologies, with proven debugging capabilities.
• Proficient with Synopsys, Cadence, and Mentor simulators along with associated debugging tools.
• Experience in low power and formal verification is advantageous.
• Advanced UNIX scripting skills using Python, Perl, makefile, and C shell.
• A quick learner who adapts effectively to emerging technologies.
• Preference for Singapore citizens and Permanent Residents.