Senior Physical Design Implementation Engineer

About the Role

Join a leading global semiconductor company as a Senior Physical Design Implementation Engineer. This position is based in Cork, County Cork, Ireland, and requires expertise in the comprehensive physical design flow for ASIC and SoC technologies.

Key Responsibilities & Requirements

• Possess at least four years of practical experience in physical design engineering.
• Manage the complete physical design lifecycle, including netlist handoff, floorplanning, power planning, placement, clock tree synthesis (CTS), routing, and design optimization.
• Utilize state-of-the-art physical design tools tailored for advanced nodes at 10nm technology and below, covering both implementation and signoff stages.
• Have an in-depth understanding of Static Timing Analysis (STA), timing closure methodologies, and awareness of how timing affects routing congestion, power consumption, and overall routing quality.
• Be knowledgeable in power analysis methods and power integrity assessment techniques.
• Have practical experience with physical verification workflows aimed at achieving Design Rule Check (DRC) clean layouts.

Additional Information

Relevant keywords linked with this position include ASIC, Physical Design, System-on-Chip (SoC), RTL-to-GDS flow, Place and Route, Static Timing Analysis, IP and Digital Design, Cadence, Synopsys tools, Semiconductor industry, Timing Closure, and Performance-Power-Area (PPA) optimization.

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