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Staff CAD Engineer – GPU / PPA / RTL-to-GDS / EDA / Methodology

European Tech Recruit

Cork Metropolitan Area · Full Time

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Experience
5–7 yrs
Salary
—
Openings
1
Posted
3 days ago
Work mode
In office
Resume
Required to apply

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Job description

Position Overview

We are collaborating with a cutting-edge technology company focused on the development of advanced GPU cores and are seeking a Staff CAD Engineer. This role is dedicated to designing and enhancing flows, methodologies, and algorithms that optimize power, performance, and area (PPA) within GPU development.

Roles and Responsibilities

  • Create and enhance CAD flows, methodologies, and algorithms aimed at increasing PPA efficiency for GPU cores.
  • Work in close partnership with graphics microarchitecture design and implementation teams to support GPU development.
  • Maintain and improve ASIC design processes spanning from RTL to GDSII stages.
  • Participate in developing methodologies specific to GPU implementation.
  • Recognize and act upon opportunities to streamline flows and procedural improvements.
  • Assist in managing design constraints, including power, timing, clocking, and interfaces to ensure robust implementation.
  • Contribute to formal verification efforts, including RTL-to-netlist and netlist-to-netlist checks.

Qualifications and Experience

  • Between 5 to 7 or more years of expertise crafting methodologies focused on PPA enhancements.
  • Fundamental understanding of digital design principles and RTL development.
  • Familiarity with the comprehensive ASIC design journey from RTL through to GDSII.
  • Knowledge of synthesis, static timing analysis, formal verification, physical design, ECO generation, and verification processes.
  • Proficiency in Verilog and SystemVerilog languages.
  • Experienced in RTL synthesis employing physically aware synthesis tools.
  • Skilled in managing design constraints related to power, timing, clocking, and interfaces.
  • Hands-on experience in delivering GPU core implementations progressing from RTL to GDSII.
  • Experience with semi-custom design flows and the development of related methodologies.
  • Practical use of Synopsys Fusion Compiler, RTL Architect, PrimePower, PrimeTime, and Prime Closure tools.

Additional Notes

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