STA Design Engineer - ASIC / Low Power

About the Role

We are collaborating with a leading global firm in semiconductor and wireless technologies that specializes in delivering high-performance, low-power ASIC products for advanced cores and System-on-Chips (SoCs). This position is for a permanent role based in Cork, Ireland. The STA Design Engineer will manage intricate timing signoff processes and ensure timing closure for state-of-the-art products.

Key Responsibilities

• Conduct Static Timing Analysis (STA) and lead timing closure efforts on complex cores and complete chip SoCs, such as those in the Snapdragon portfolio.
• Assess timing at both block and top levels using gate-level post-route netlists.
• Collaborate closely with RTL, Synthesis, and Physical Design groups to enhance Power, Performance, and Area (PPA) metrics.
• Develop and execute Timing Engineering Change Orders (ECOs) to fix critical timing violations.
• Innovate and refine timing closure techniques and STA workflow to improve accuracy and reduce turnaround time.
• Create automation scripts in Python, TCL, or Perl to process timing and power data efficiently.

Required Qualifications and Experience

• Minimum of 4 years professional experience in Static Timing Analysis.
• Advanced skills using STA tools such as PrimeTime, PrimeShield, or Tempus for hierarchical timing analysis in large SoC designs.
• Practical knowledge of ECO tools like Tweaker, PrimeClosure, PTECO, and Tempus ECO for achieving timing closure.
• Strong scripting expertise in Python, TCL, or Perl to support automation in timing and power data mining.
• Comprehensive understanding of the ASIC design process from RTL to GDS layout.

Additional Information

Applicants acknowledge that their personal information will be collected and processed in accordance with company privacy policies. This role is ideal for individuals specializing in STA, ASIC design, and SoC development looking to contribute to cutting-edge semiconductor projects.