Senior Design Verification Engineer

Overview

Our client, a leading innovator in technology, is committed to advancing the frontiers of communication and data processing to create intelligent and interconnected experiences. They are currently seeking a skilled Verification Engineer to enhance their team and contribute to next-generation solutions.

Key Responsibilities

• Implement advanced verification methodologies, including Universal Verification Methodology (UVM) and formal verification techniques.
• Design and develop testbenches, verification components such as UVCs, and reusable verification environments both vertical and horizontal.
• Conduct RTL verification of sensor algorithms to guarantee ASIC tapeout readiness.
• Create thorough test plans aligned with design specifications while collaborating closely with design and systems teams.
• Integrate C language models into UVM-based verification frameworks to enhance verification coverage.
• Write SystemVerilog assertions to ensure design integrity and correctness.
• Perform design debugging, verification, and optimization, confirming bit-accurate results compared to reference vectors.
• Analyze coverage data, identify gaps, and coordinate with design teams to improve coverage metrics.
• Develop and refine regression testing frameworks, troubleshoot failures, and collaborate with cross-functional stakeholders.
• Support subsystem integration efforts, including planning, vector management, and debugging activities.
• Create Python-based automation tools to streamline workflows and increase team productivity.
• Engage in project review meetings and contribute technical insights.
• Assist software and interdisciplinary teams with debugging tasks.
• Maintain detailed and clear technical documentation of verification processes and results.

Qualifications

• Bachelor’s degree in Science, Engineering, or a related discipline.
• Minimum of three years’ experience in ASIC design verification or functional verification using UVM or equivalent methodologies.
• Deep knowledge of constrained-random and coverage-driven verification strategies.
• Proficiency in UVM, SystemVerilog, and the development of SystemVerilog Assertions.
• Experience with RTL simulation tools and effective debugging practices to fulfill coverage objectives.
• Competency in scripting languages such as Python, Perl, or shell scripting.
• Familiar with C/C++ programming languages.
• Exceptional analytical, problem-solving, and collaborative capabilities suited for dynamic work environments.
• Strong communication skills both written and verbal.

Preferable Skills

• Practical experience with formal verification tools like Jasper or VC Formal.
• Exposure to SystemC and MATLAB environments.
• Knowledge of gate-level simulation, debugging, and power analysis techniques.

Additional Information

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