Senior AI Engineer – Design Automation

About the Role

Based in Singapore, this role involves leveraging advanced artificial intelligence methods to expedite the development of chips that are faster, more compact, and energy efficient.

Core Responsibilities

• Utilize Large Language Models (LLMs) to autonomously create, enhance, and debug Register Transfer Level (RTL) code written in Verilog and SystemVerilog.
• Employ Graph Neural Networks (GNNs) to evaluate chip netlists for early identification of physical design challenges such as wiring and spacing constraints.
• Design AI-driven autonomous agents that can operate Electronic Design Automation (EDA) tools, interpret output data, diagnose errors, and implement corrective measures with limited human input.
• Convert state-of-the-art academic research in AI-assisted EDA into reliable, industry-ready software that supports silicon engineering teams.

Qualifications and Skills

• Doctorate degree (Ph.D.) in Computer Science, Artificial Intelligence, Machine Learning, or closely related disciplines.
• Engagement in research activities—thesis or publications—in Graph Machine Learning, code and hardware description languages optimization (Verilog/SystemVerilog), or natural language processing applied to code.
• Familiarity with conventional VLSI design processes including synthesis, static timing analysis, and physical layout design is advantageous.
• Advanced expertise in PyTorch, PyTorch Geometric (PyG), and contemporary Large Language Model frameworks.
• Proficient programming ability in Python.

Additional Information

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