Semiconductor Design Verification Engineer

Job Overview

This role is based in Singapore and involves a deep understanding of digital design specifications for various IP blocks and SoC architecture. The successful candidate will be responsible for developing detailed test plans, building comprehensive ASIC verification environments, and executing verification strategies to ensure functional correctness.

Responsibilities

• Create detailed module-level and SoC-level test plans covering all functional aspects derived from design specifications.
• Develop ASIC verification environments comprising stimuli, checkers, assertions, monitors, and scoreboards.
• Generate both directed and constrained-random verification functional tests and conduct simulations using EDA tools to validate functionality.
• Execute verification plans including design initialization, DV bring-up, and regression enabling across all features.
• Work collaboratively with the digital design team to debug functional test cases and ensure design functionality.

Qualifications and Experience

• Possess a Bachelor's or Master's degree in Electronics or Electrical Engineering.
• Minimum of six years of experience in SoC/IP verification.
• Excellent communication, analytical, and documentation skills capable of interfacing with cross-functional groups.
• Extensive VLSI functional verification experience, especially with complex high-speed custom VLSI products.
• Proficient in hardware functional verification languages and object-oriented programming.
• Strong expertise in SystemVerilog, UVM, and Python; knowledge of TCL and Perl is advantageous.
• Familiarity with ASIC verification methodologies, tools, and workflows.
• Experience with Automotive SoCs, Ethernet/Switch IPs, High-Speed IOs, Memory Controllers (DDR, PSRAM, Flash), Video interfaces (MIPI, CSI, DSI, HDMI, DP) is a significant plus.
• Ability to work independently, estimate effort requirements accurately, and meet deadlines.
• Active participation in troubleshooting and resolving verification issues throughout the project lifecycle.
• Contribution towards enhancing verification practices at both IP and SoC levels.