Physical Design Engineer

Role Summary

We are seeking a seasoned Physical Design Engineer to operate from our Bangalore or Hyderabad locations. Candidates with 6 to 10 years of experience in physical design implementation are preferred and should be available to join immediately or within a notice period of up to 60 days.

Key Responsibilities

• Independently manage the execution and delivery of medium to complex full chip or block RTL-to-GDS implementations.
• Conduct power, performance, and area (PPA) analysis and develop strategies for improvement.
• Play an active role in multiple tape-outs across various technology nodes, including advanced Intel lower nodes such as 18A.
• Apply expertise in IO planning, including package interfaces, ESD design, and multi-voltage sequencing.
• Perform hierarchical design partitioning and employ hierarchical flow methodologies.
• Engage in power estimation, planning, and analysis, covering static and dynamic IR drop and electromigration (EM).
• Handle floor planning, placement, congestion management, timing closure, clock tree synthesis (CTS), and post-CTS flows.
• Ensure manufacturability by executing physical verification steps like DRC, LVS, and GDS checks.
• Contribute to schedule recovery efforts, mentor team members, and engage in customer communication.
• Demonstrate knowledge or exposure to synthesis, static timing analysis (STA), design for test (DFT), logical equivalence checking (LEC), and voltage controlled logic partitioning (VCLP).
• Utilize industry-standard EDA tools primarily from Synopsys and Cadence.
• Implement and verify low-power design techniques.
• Employ TCL scripting for automation and process optimization.

Additional Information

The notice period expected is immediate to 60 days. The work location is either Bangalore or Hyderabad.