DFT Engineer

Job Overview

We are seeking an experienced DFT Engineer with a minimum of six years of expertise in Design for Test (DFT) focusing on System on Chip (SoC) and modem technologies used in smartphones. The role involves collaborating closely with smartphone SoC teams, optimizing test pattern generation and coverage, and contributing to DFT methodologies for advanced technology nodes.

Key Responsibilities

• Perform ATPG coverage analysis and implement improvements for smartphone SoC/modem designs.
• Generate and optimize ATPG/TFT test patterns to enhance test effectiveness.
• Plan and coordinate SoC and modem DFT requirements alongside smartphone SoC teams.
• Manage pre-silicon DFT verification activities and troubleshoot post-silicon DFT issues.
• Design DFT clocking schemes and manage timing constraints to ensure performance.
• Conduct scan synthesis, analyze and stitch scan chains effectively.
• Implement DCT/DCG synthesis and assist in analyzing timing violations with STA teams.
• Develop and apply DFT methodologies aligned with new semiconductor technology nodes.

Candidate Qualifications

• A minimum of six years working experience in DFT, particularly using tools such as Tetramax.
• Proven experience with SoC and modem DFT related to smartphone platforms.
• Competence in ATPG coverage analysis and test pattern optimization.
• Experience in handling both pre-silicon verification and post-silicon debugging of DFT circuits.
• Strong skills in scan synthesis, scan-chain stitching, clocking, and timing constraints management.
• Knowledge of DCT and DCG synthesis processes.
• Collaboration experience with Static Timing Analysis (STA) teams to resolve timing issues.
• Up-to-date expertise with DFT methodologies tailored to emerging technology nodes.