Associate Staff Implementation Design Engineer

About Silicon Labs

Silicon Labs (NASDAQ: SLAB) is a pioneer in low-power wireless connectivity, developing embedded technologies that connect devices and enhance lives. Combining advanced technology with the industry's most integrated SoCs, Silicon Labs offers solutions, support, and ecosystems that empower device makers to build sophisticated edge connectivity applications. The company is headquartered in Austin, Texas, with operations in more than 16 countries and trusted as a partner in smart home, industrial IoT, and smart city sectors.

Role Overview

We are looking for a highly experienced Associate Staff Design Engineer to join our Silicon Engineering team in Singapore. This position involves leadership and hands-on involvement across various phases of backend (BE) implementation, including synthesis, static timing analysis (STA), logic equivalence, and low-power verification. You will be accountable for developing constraints and ensuring timing closure for high-performance SoCs and ASICs across multiple modes and process corners. The ideal candidate has comprehensive experience in the full BE implementation flow, including synthesis, placement & routing, logic equivalence, UPF and low power checks, STA, and power voltage signoff, and is capable of leading full backend implementation for advanced SoCs using physical design methodologies. Expertise in power, performance, and area (PPA) optimization along with low power implementation methods is essential.

Key Responsibilities

• Lead and execute the full RTL-to-GDSII implementation flow managing timing constraints jointly with design and DFT teams.
• Take ownership of STA runs for both digital blocks and top-level chip designs.
• Coordinate with design and physical design teams to develop clock tree synthesis (CTS) specifications.
• Conduct logical equivalence verification using industry-standard tools.
• Develop and execute low-power verification and UPF methodologies.
• Interpret timing reports and perform timing fixes including ECOs to address critical paths.
• Enhance timing methodologies and automate backend processes to improve efficiency.
• Perform timing checks related to CDC, false paths, and multi-cycle scenarios.
• Lead a team to deliver complex SoCs and IP blocks through all physical design stages—from RTL handoff to GDSII.
• Optimize power, performance, and area metrics for assigned designs.
• Manage design constraints, synthesis strategies, and sign-off criteria encompassing timing, electromigration drop, IR drop, and physical verification checks.
• Work collaboratively with front-end RTL, DFT, verification, and packaging groups to ensure seamless integration.
• Drive automation of EDA tool flows and methodological improvements to increase scalability and workflow efficiency.
• Mentor junior engineers, fostering their technical development and promoting design excellence.

Candidate Requirements

• Bachelor’s or Master’s degree in Electrical and Computer Engineering (ECE), Electrical and Electronics Engineering (EEE), VLSI, or a related discipline.
• 9 to 10 years of hands-on experience in ASIC physical design.
• Proficient with industry leading EDA tools such as Cadence (Genus, Innovus, Tempus, LEC, CLP) or Synopsys (ICC2, Fusion Compiler, PrimeTime).
• Strong expertise in synthesis processes, constraints management, timing margin analysis, and resolving timing failures.
• Knowledge and experience in low-power design methodologies including UPF/CPF, power gating, and DVFS.
• Thorough understanding of the architecture through to GDSII flow including all necessary sign-off requirements.
• Excellent analytical, problem-solving, and communication abilities.

Preferred Qualifications

• Experience with hierarchical design and chip-level integration methodologies.
• Familiar with DFT, floorplanning, placement and routing, and physical verification including IR drop analysis.
• Exposure to complex designs involving multiple clocks, voltages, and operating domains.
• Proven leadership experience managing small teams between 4 to 10 members within this domain.
• Automation skills using scripting languages such as Perl, TCL, TK, and Python.
• Experience working in multi-site and collaborative environments.

Benefits

• Comprehensive medical and dental insurance coverage including dependents (spouse and children).
• Biannual health screening and seasonal flu vaccination programs.
• Convenient office location with easy access above Tai Seng MRT station.

Diversity and Inclusion

Silicon Labs is committed to equal opportunity employment and values staff diversity. Hiring decisions are made based solely on qualifications and job relevance without regard to race, religion, color, gender, sexual orientation, age, or other protected statuses under applicable laws.