Technology Lead - Memory Layout
Vancouver, British Columbia, Canada · Full Time
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- Experience
- 4+ yrs
- Salary
- CAD 90,450 – CAD 136,500 / year
- Openings
- 1
- Posted
- 4 days ago
- Work mode
- In office
- Education
- Bachelor’s degree or equivalent
- Eligibility
- Candidates must be located within commuting range of Vancouver, BC, or willing to relocate. Must be authorized to work in Canada without employer sponsorship. Travel within Canada may be required.
- Resume
- Required to apply
Where you'll work
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Job description
About the Role
Infosys is seeking a skilled Technology Lead specialized in Memory Layout design to join our team. You will collaborate closely with engineers focused on Registers, Memory Arrays, and Memory Data Path layout and design, using schematics as a foundation to progress design initiatives in partnership with circuit teams to develop optimal layouts.
Key Responsibilities
- Work alongside circuit engineers to advance memory layout projects based on provided schematics.
- Design and integrate memory leafcell layout libraries from the ground up including top-level integration tasks.
Required Qualifications
- Must reside within commuting distance to Vancouver, BC, Canada or be willing to relocate; travel within Canada may be required.
- Bachelor's degree or a foreign equivalent from an accredited institution is required; alternatively, three years of progressive experience in place of each year of education.
- A minimum of four years' experience in Information Technology.
- Authorized to work for any employer in Canada without requiring employer-sponsored visa; Infosys does not provide immigration sponsorship for this role.
Essential Skills
- At least five years of hands-on experience in Compiler and Custom Memory Layout design.
- Expertise in designing memory leafcell layout libraries including top-level integration.
- Strong understanding of various memory architectures.
- Proficiency in optimized layout design techniques aimed at enhancing performance.
- In-depth experience with FinFET technology, layout design constraints, and DRC limitations.
- Exposure to advanced fabrication processes including 3nm and 5nm technologies.
- Competence in physical verification processes such as DRC, LVS, ERC, and boundary condition checks, including debugging.
- Proficient with Cadence Virtuoso layout editor and Calibre physical verification tools.
Additional Information
The position requires the ability to sit and work on a computer for extended durations. Effective communication through phone, email, and face-to-face interactions is essential.
Compensation
An estimated annual salary range for candidates based in British Columbia is between $90,450 and $136,500.
About Infosys
Infosys is a global leader in next-generation digital services and consulting, partnering with clients in over 50 countries to drive their digital transformations. Drawing on over forty years of global enterprise experience, we facilitate AI-powered core capabilities and agile digital solutions at scale to enhance performance and customer satisfaction. Our continuous learning culture promotes skill development through our extensive innovation ecosystem.
Equal Employment Opportunity
Infosys is committed to providing equal opportunity in employment regardless of race, color, sex, gender identity, sexual orientation, religion, national origin, pregnancy status, veteran status, disability, or any other protected status.
Minimum education
Bachelor's Degree