Static Timing Analysis (STA) Lead Engineer

Overview

Join a cutting-edge Silicon Valley storage startup as the Static Timing Analysis (STA) Lead Engineer in Bangalore, India. You will lead timing closure efforts for complex, high-performance ASICs utilizing advanced technology nodes including 16, 12, 7, and 5 nanometers.

Qualifications and Experience

• Bachelor's degree in Electrical/Electronics Engineering or VLSI, Master's degree preferred.
• More than 10 years of hands-on experience in STA using industry-standard Synopsys PrimeTime tools.
• Solid foundation in digital ASIC design principles.
• Comprehensive understanding of SoC design methodologies and challenges.
• Familiarity with design flows such as synthesis, constraint creation, functional and DFT mode STA, and physical design.
• Proficiency with implementation tools including Synopsys PrimeTime, Design Compiler, and Fusion Compiler at both block and chip (top) level.
• Capability with scripting languages TCL and Perl for flow automation.
• Strong communication skills and proven ability to collaborate effectively within teams.

Key Responsibilities

• Develop and enhance STA methodologies and flows.
• Create and integrate constraints at block and SoC levels to support timing closure.
• Deliver early detection and recommendations for design and timing issues.
• Collaborate with backend physical design teams during place and route (PnR) to achieve timing closure.
• Partner with IP and SoC design teams to optimize timing and design implementation.
• Manage timing closure activities across blocks and the entire SoC, covering all operational modes and process corners, including implementing timing Engineering Change Orders (ECOs).