STA Design Engineer - ASIC and Low Power

Position Overview

We are working with a prominent global semiconductor and wireless technology leader specializing in high-performance, low-power ASIC solutions targeting advanced cores and system-on-chips (SoCs). Our team seeks to recruit a skilled STA Design Engineer responsible for executing intricate timing signoff activities and ensuring timing closure for upcoming products. This permanent role is based onsite in Cork, Ireland.

Primary Duties

• Conduct Static Timing Analysis (STA) and facilitate timing closure for complex cores and full-chip SoCs, such as those in the Snapdragon series.
• Assess timing at both block and top hierarchical levels using gate-level placement and routing netlists.
• Provide essential input to RTL, synthesis, and physical design teams to enhance Power, Performance, and Area (PPA) metrics.
• Generate and implement Engineering Change Orders (ECOs) related to timing to address critical violations.
• Refine methodologies and tools to improve timing closure workflows and STA accuracy, thereby reducing turnaround times.
• Create automation scripts using Python, TCL, or Perl for mining and handling timing and power-related data.

Candidate Profile

• At least four years of experience in Static Timing Analysis within ASIC design.
• Proficient with STA tools such as PrimeTime, PrimeShield, or Tempus specifically for hierarchical timing analysis of large SoCs.
• Practical experience using ECO tools like Tweaker, PrimeClosure, PTECO, or Tempus ECO for resolving timing closure challenges.
• Advanced scripting capabilities in Python, TCL, or Perl for automation related to timing and power data processing.
• Comprehensive understanding of the entire ASIC design flow from RTL to GDS.

Additional Information

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