Senior Timing Engineer

About the Role

Join Qualcomm, a global leader pushing technological frontiers to enable next-generation communication and data processing experiences. As a Senior Timing Engineer, you will be responsible for modeling, designing, optimizing, validating, and documenting IP and SoC blocks for high performance, energy-efficient products. You will collaborate with various cross-functional teams to successfully execute product development strategies.

Primary Responsibilities

• Leverage ASIC expertise to define, design, optimize, verify, and implement digital and analog IP blocks.
• Develop architectures, create circuit specs, design logic, and conduct system simulations based on overarching system requirements.
• Collaborate with software and hardware architecture teams to devise and execute implementation plans meeting both system goals and customer needs.
• Assess the entire design flow including synthesis, place and route, static timing analysis, power usage, and verification.
• Utilize EDA tools like RTL-to-GDS flows and Virtuoso for architecture and individual block or package level design.
• Document detailed technical specifications and project reports related to EDA, IP, and ASIC developments.

Key Qualifications and Experience

• Strong background in timing-related activities such as library characterization, LVF, AOCV/POCV/SOCV analysis.
• Proficient with CAD tools and comprehensive correlation between timing sign-off tools and Spice simulation, covering timing, noise, and Monte-Carlo analyses.
• In-depth knowledge of standard cell library characterization processes and workflows.
• Automation and flow development skills using scripting languages including Python, Perl, TCL, and Bash.
• Practical experience with Spice extraction, modeling, and aging reliability models on advanced technology nodes.
• Sound understanding of physical design methodologies, including Place and Route and Static Timing Analysis (STA) sign-off techniques.
• Willingness to learn, develop, and validate new methodologies continuously.

Educational and Professional Requirements

• Bachelor's degree in Science, Engineering, or a related discipline with a minimum of 2 years ASIC-related work experience.
• Or a Master's degree in a relevant field with at least 1 year of related experience.
• Alternatively, holders of a PhD in a related technical field are also encouraged to apply.
• Preferred: Master's degree in Electrical/Electronic Engineering, Computer Engineering, or Computer Science.
• Demonstrated 3+ years ASIC design, verification, validation, or integration experience.
• At least 2 years experience with architecture and design tools, scripting languages, and design verification methods.

Work Environment and Location

This role is based in Cork, Ireland, renowned for its vibrant economy and diverse international community. Cork offers an excellent standard of living and convenient access to nearly 50 global destinations via its international airport.

Equal Opportunity and Inclusivity

Qualcomm is committed to creating an inclusive workplace and provides reasonable accommodations for applicants with disabilities during the hiring process.

Compensation and Benefits

• Competitive salary with stock options and performance bonuses.
• Parental leave including maternity and paternity.
• Employee stock purchase and matching pension schemes.
• Support for relocation and immigration, where applicable.
• Comprehensive insurance plans covering life, medical, income protection, and travel.
• Subsidized wellness memberships and bicycle purchase program.
• Employee-led clubs for activities like running, football, chess, and badminton.
• Education assistance opportunities.

Additional Information

Applicants must abide by Company policies, especially those concerning confidentiality and proprietary information. Qualcomm does not accept unsolicited resumes from recruiting agencies.