Senior Physical Design Engineer

About Bitdeer

Bitdeer is a leading global technology company specializing in Bitcoin mining and AI cloud services. The company offers comprehensive mining solutions, including ASIC chip design, manufacturing mining rigs, and managing the entire value chain such as equipment procurement, logistics, datacenter development, and network operations. Headquartered in Singapore, Bitdeer manages a diversified 3 GW energy portfolio with mining and HPC data centers spread across various countries including the USA, Bhutan, Norway, Canada, Malaysia, and Ethiopia.

Role Overview

We seek an experienced Senior Physical Design Engineer to lead the physical implementation of high-speed PCIe IP and subsystem for AI chips. The candidate will manage the complete physical design flow from netlist to final GDSII delivery. The role requires close collaboration with teams specializing in circuit design, DFT, and verification to produce silicon-verified, high-performance designs on advanced process nodes.

Core Responsibilities

• Manage the entire physical design process including floorplanning, placement, clock tree synthesis (CTS), routing, static timing analysis (STA), physical verification, and final signoff for PCIe controller and PHY blocks.
• Achieve timing closure for high-speed PCIe Gen 4/5/6 interfaces under all PVT (process, voltage, temperature) conditions.
• Conduct power integrity assessments such as IR drop and electromigration analysis across the power delivery network.
• Complete physical verification closures including DRC, LVS, and ERC signoff utilizing Calibre tools.
• Collaborate with RTL and synthesis teams to suggest logic restructuring for improved timing and area efficiency.
• Contribute to enhancement of internal physical design methodologies, scripting, and automation using Perl and Tcl languages.
• Support tapeout processes including GDS merge, fill insertion, and final signoff validation.

Qualifications & Requirements

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related fields.
• Minimum of 5 years hands-on experience in physical design on advanced TSMC nodes (preferably N6 or below).
• Comprehensive understanding of PCIe protocol and design constraints for high-speed interfaces.
• Proficient in CTS strategies including skew balancing, useful skew, and multi-corner timing closure for high-speed designs.
• Practical experience using industry-leading PnR and timing signoff tools such as Cadence Innovus, Synopsys Primetime, and Tweaker.
• Expertise in addressing chip-level DRC, LVS, and EMIR issues for advanced technology nodes.
• Experience with multi-die packaging techniques (WoW, 2.5D/3D), thermal/IR/EM signoffs, signal integrity, and DFT-aware physical design is beneficial.
• Familiarity with scripting languages including Python, Perl, Tcl, and Make.
• Prior tapeout experience is mandatory.

Work Environment & Culture

• Inclusive culture embracing authenticity and diversity of thought.
• Open workspaces fostering collaboration and startup energy.
• Opportunities to engage with industry pioneers and to influence the digital asset sector’s advancements.
• Participation in innovative projects and process development.
• Emphasis on personal responsibility, autonomy, rapid development, and continuous learning.
• Access to attractive benefits and growth opportunities including training and mentoring.

Equal Opportunity Statement

Bitdeer is dedicated to equal employment opportunities and abides by all applicable laws to prohibit discrimination on the basis of race, color, gender identity or expression, sexual orientation, marital or parental status, religion, political opinions, nationality, ethnicity, social origin or status, disability, age, indigenous status, or union membership.