Principal Verification Engineer

About the Role

A prominent semiconductor IP company is seeking an experienced Principal Verification Engineer to enhance the development of advanced memory controller IP, vital for data-heavy and future compute applications.

Key Responsibilities

• Architect and define scalable UVM-based verification environments tailored to intricate controller IPs.
• Create self-validating testbenches, maintain scoreboards, and develop coverage models to facilitate verification driven by metrics.
• Design and implement assertions suitable for both simulation and formal verification techniques.
• Manage and uphold verification plans, ensuring they align precisely with specifications and coverage goals.
• Lead regression strategies and automate processes in conjunction with CAD and flow teams.
• Collaborate closely with RTL designers to troubleshoot and resolve complex corner-case design issues.
• Participate in technical reviews and contribute to quality assurance procedures throughout the product development life cycle.

Candidate Profile

• Proven expertise with SystemVerilog and UVM methodologies within production settings.
• Extensive background in verifying complex digital IP or SoC subsystems.
• Strong foundation in RTL design concepts alongside effective debugging techniques.
• Hands-on experience with coverage-driven verification methods.
• Familiarity with AMBA protocols such as AXI or CHI is advantageous.

Additional Information

This senior-level position requires a candidate capable of shaping verification methodologies and offering guidance to junior team members.