Principal Engineer - IP Verification

Overview

We are looking for a highly motivated and energetic Principal Engineer specializing in Digital IP Verification with 10 to 15 years of experience. This role demands an individual contributor who embraces challenges to achieve first-pass success for complex Vision and Image Processing IPs, utilizing the most advanced verification languages and methodologies.

Responsibilities

• Deploy and assess advancing verification methodologies to manage increasingly intricate IP and Subsystem designs within tight market-driven schedules.
• Take ownership and guarantee adherence to quality standards throughout all project phases, analyze current processes, and suggest and implement enhancements aimed at achieving zero defect IPs and subsystems.
• Drive and influence technological innovation for oneself and within team environments.
• Collaborate effectively as part of both local and distributed, multi-site teams.

Requirements and Skills

• Proven self-starter with 10 to 15 years’ experience in IP and Sub-system verification for multimillion gate designs featuring multiple clock domains, performing with minimal supervision.
• Expertise in developing testbenches and test plans ensuring comprehensive functional verification, IP performance evaluation, and feature traceability.
• Experience with microcontroller architectures, particularly ARM cores, and protocols such as AHB/AMBA, AXI, along with memory types including Flash, SRAM, DDR, and memory controllers.
• Knowledge of automotive domains including Graphics and Vision accelerators, serial IP controllers at both slow and high speeds, and networking protocols like Ethernet is an advantageous plus.
• Strong proficiency in Hardware Verification Languages (HVLs) like UVM, SystemVerilog, C++ and Hardware Description Languages (HDLs) such as Verilog and VHDL; also familiar with PLI/DPI interfaces and simulators including NCSim, VCS, ModelSim, and Questa.
• Comprehensive experience managing the entire IP verification lifecycle, from testbench strategy and development through simulation debugging.
• Good familiarity with formal verification methodologies including assertions and SVA, functional coverage, gate-level simulations, verification planning, and regression management.
• Demonstrated capability to lead verification methodology initiatives, particularly for candidates with over 10 years of experience.
• Exposure to pre-silicon validation or emulation adds value.

Additional Information

This role involves collaborating closely with teams across systems, design, design-for-test (DFT), mixed-signal specialists, and various local and remote groups to tackle verification challenges at IP, subsystem, and system levels through simulation, hardware modeling, formal verification, and active engagement in pre- and post-silicon validation.

NXP Semiconductors India is the hiring organization, located in Noida, Uttar Pradesh, India, offering a full-time position with remote work flexibility.