Mixed-Signal Design Verification Engineer

About the Role

Qualcomm’s Mixed-Signal IP (MSIP) Design Verification team in Cork, Ireland is looking for skilled engineers to join their team. The successful candidate will focus on verifying mixed-signal physical interface (PHY) IPs such as DDR, USB, PCIe, eDP, DPRX, HDMI, SGMII, DSI, CSI, PLL and more. The Cork site is home to several advanced MSIP teams working on innovative designs for the latest Snapdragon System on Chips (SoCs) using cutting-edge technology nodes down to 3nm and beyond.

The selected engineer will collaborate closely with architecture, design, software, and SoC teams both locally and globally to ensure the quality and integration of various mixed-signal PHY IP blocks.

Key Responsibilities

• Develop and execute SystemVerilog/UVM based design verification for SerDes, DDR, and PLL mixed-signal PHY IPs.
• Utilize emulation and simulation tools to validate IP functionality.
• Work alongside analog and digital front-end design teams to verify RTL and mixed-signal designs within next-generation SerDes, DDR, and PLL IPs.
• Engage with teams across architecture, design, physical design, software, testing, and SoC development to integrate verified IPs into Qualcomm Snapdragon products.

Qualifications and Experience

• Bachelor’s degree in Engineering, Computer Science, Science, or related disciplines.
• Minimum of 2 years experience in design verification or similar roles.
• Expertise in hardware and software design verification methodologies for SoCs and IP blocks, using industry-standard verification tools.
• Proficient in creating UVM-based unit and SoC/IP level test benches.
• Strong knowledge of constrained random functional verification environment in SystemVerilog/UVM with excellent debugging capabilities.
• Experience in low power verification using Unified Power Format (UPF) at RTL and gate-level simulation (GLS).
• Familiarity with power-aware gate level simulation flows including zero delay and Standard Delay Format (SDF) annotated simulations.
• Hands-on experience with pre- and post-silicon verification flows, automated test benches, and post-silicon ATE/PTE vector bring-up and bench characterization.
• Understanding of test-plan development, coverage metrics (code and functional), transaction-level modeling, assertion-based verification, and formal verification techniques with SystemVerilog.
• Programming and scripting experience in Verilog, SystemVerilog, assertions, Python, TCL, Perl, and shell scripting.
• Prior knowledge of analog mixed signal verification techniques is an advantage.
• Excellent verbal and written communication skills.

Work Environment and Location

This position is based in Cork, Ireland, a thriving hub for over 170 international companies employing approximately 39,000 people. Cork offers a vibrant multicultural community, strong transport connections including Cork Airport with nearly 50 international destinations, and an exceptional quality of life.

Benefits and Additional Information

• Competitive salary along with stock options and performance bonuses.
• Parental leave including maternity and paternity benefits.
• Employee stock purchase plan and matching pension scheme.
• Support for education, relocation, and immigration if required.
• Comprehensive insurance coverage including life, medical, income, and travel.
• Subsidized memberships promoting physical and mental wellness.
• Bicycle purchase support and diverse employee-run clubs such as running, football, chess, and badminton.

Equal Opportunity

The employer is an equal opportunity organization. Applications are welcome irrespective of race, color, religion, sexual orientation, gender identity, national origin, disability, veteran status or other protected categories. Reasonable accommodations for applicants with disabilities are available upon request during the hiring process.

Recruitment Policy

The employer does not accept unsolicited resumes from recruitment agencies and asks agencies not to forward resumes or applications to the company or its employees. Candidates must apply directly.