DSP / NPU Staff Design Verification Engineer

About Qualcomm

Qualcomm India Private Limited is a leading innovator in technology striving to push the limits of digital transformation, enabling smarter, connected experiences worldwide. The Engineering Group's Hardware Engineering team works on designing, verifying, optimizing, and testing electronic and digital systems including DSP, FPGA, mechanical and packaging systems to deliver industry-leading products.

Role Overview

This position requires a seasoned engineer with over 12 years of experience focused on design verification of complex proprietary DSP and NPU intellectual property. The role contributes to Qualcomm's roadmap targeting high-performance DSP/NPU cores for mobile, AI, automotive, and other sectors.

Key Responsibilities

• Lead design verification efforts of DSP IP in collaboration with global teams including architecture, implementation, power, post-silicon, and backend groups.
• Design, enhance, and maintain SystemVerilog/UVM testbench architectures.
• Develop and implement new verification methodologies and automation tools to elevate verification quality and efficiency.
• Create detailed test plans and verification environments aligned with design requirements, ensuring coverage goals are met.
• Perform simulations and troubleshoot issues from IP to subsystem and SoC level.
• Execute all IP-level verification activities ensuring the delivery of robust products.
• Utilize assertion-based verification, formal verification tools, hardware-software co-verification, constraint-based verification, simulation acceleration, and emulation techniques regularly.
• Manage gate-level simulation bring-up and verification incorporating timing and power aspects.
• Conduct power-aware RTL and gate-level verification.

Required Skills and Qualifications

• Bachelor’s degree in Computer Science, Electrical/Electronics Engineering or related field with at least 6 years, or Master’s with 5 years, or PhD with 4 years of relevant hardware engineering experience.
• Extensive experience (12+ years) in processor or ASIC design verification.
• Strong foundation in digital design, processor architecture, power-aware verification techniques, and processor verification.
• Advanced knowledge of SystemVerilog testbench architecture and implementation, including UVM.
• Preferable experience developing C-based and assembly-level test cases.
• Familiarity with power-aware implementation/verification using UPF is advantageous.
• Experience in formal verification methods and assertions is beneficial.
• Proficient in gate-level simulation and debugging, including zero-delay, timing-annotated, and power-aware simulations.
• Hands-on knowledge of SystemVerilog/UVM and simulators from vendors like Synopsys, Mentor, and Cadence.
• Scripting skills in Perl, Python, Shell scripting, and automation using Makefiles or TCI.
• Strong analytical, debugging skills and solid understanding of object-oriented programming principles.
• Experience with hardware verification languages, such as SystemC, and hardware description languages like Verilog is preferred.
• Prior experience verifying processor subsystems and developing validation suites and automated frameworks.
• Excellent communication and interpersonal skills are essential.

Additional Information

Qualcomm is an equal opportunity employer committed to accommodating individuals with disabilities throughout the recruitment process. Applicants needing accommodations can contact the company's dedicated support. Qualcomm requires employees to comply with privacy, security, and confidentiality policies.

Agency submissions are not accepted for this position, and unsolicited applications will not be considered.