I/O Design Engineer

Role Overview

Broadcom's Central Engineering Group seeks an experienced I/O Design Engineer skilled in analog and mixed-signal integrated circuit (IC) design. The engineer will be involved in developing and verifying a wide variety of intellectual property (IP) and input/output (I/O) interfaces, including participation in cutting-edge artificial intelligence (AI) projects utilizing advanced semiconductor process nodes. The position offers a highly collaborative team environment along with prospects for career growth and skills enhancement.

Key Responsibilities

• Design CMOS I/O circuits as well as high-accuracy bandgap references, operational amplifiers, comparators, and power-on-reset components.
• Conduct simulations to ensure compliance with AC/DC parameters, signal integrity, jitter metrics, and power consumption requirements.
• Analyze transistor reliability and assess electromigration and IR-drop (EMIR) effects.
• Collaborate closely with physical layout engineers to supervise and verify chip design and layout implementations.
• Develop and maintain behavioral and timing models such as Verilog, Synopsys Liberty, and IBIS for the designed circuits.
• Produce comprehensive technical documentation including datasheets, application notes, and integration guides to support usage and characterization.
• Assist in chip-level integration activities and support silicon bring-up phases for both test chips and commercial customer products.

Qualifications and Technical Expertise

• Possession of a Master's degree or PhD in Electrical Engineering.
• Six or more years of professional experience in I/O or analog integrated circuit design.
• Proficiency with Cadence Virtuoso tools for schematic capture and layout, along with expertise in SPICE/Spectre circuit simulators.
• Strong understanding of I/O communication protocols such as GPIO, I2C, I3C, eMMC, RGMII, and SPMI.
• Experience dealing with Electrostatic Discharge (ESD), Electromagnetic Interference (EMI), and ensuring signal integrity.
• Knowledge of advanced CMOS technology processes including FinFET and Gate-All-Around (GAA) transistors, with awareness of their technology characteristics, limitations, and performance-power-area trade-offs.