IC Layout Engineer – Optical Engine Silicon

About the Role

Lumilens specializes in optical interconnect solutions for AI data centers, including silicon photonics, mixed-signal ICs, and electrical-optical interposers. Their silicon technology is actively deployed in production AI clusters and scales rapidly.

This role involves full ownership of layout design for electronic integrated circuits (EICs) and photonic integrated circuits (PICs), focusing on high-speed analog blocks where meticulous layout impacts performance and reliability. The role is based in Singapore, close to key assembly and testing supply chains, collaborating with global design teams.

Key Responsibilities

• Manage the layout process for assigned analog and mixed-signal blocks including device placement, ensuring matching and symmetry, implementing shielding, guard rings, and routing from initial floorplanning to final clean sign-off.
• Perform parasitic-aware layout adhering strictly to design constraints, conduct extraction runs, and communicate findings back to designers when discrepancies arise.
• Design high-speed signal routing with emphasis on impedance control, coupling, return paths, and passive/electromagnetic structure layout under senior guidance.
• Execute and close design rule checks (DRC), layout vs schematic (LVS), antenna and density checks; support electromigration and IR drop analyses.
• Assist with top-level assembly and chip tape-out finalization activities.
• Provide support for photonic IC layout demands, including waveguide and curvilinear structure designs.
• Lay out photonic components and precise waveguide routing based on designer inputs, ensuring adherence to minimum bend radius, spacing, phase and length matching constraints.
• Conduct photonics-specific verifications such as curvilinear DRC based on photonics process design kits (PDKs), waveguide connectivity and port validation, LVS on custom photonic cells, and ensure clean GDS output for tape-out.
• Develop scripts and reusable tools to accelerate the layout team’s workflows.

Required Qualifications

• Diploma, Bachelor's, or Master's degree in Electrical or Electronics Engineering or equivalent hands-on layout experience.
• 1 to 3 years experience in custom analog, RF, or mixed-signal IC layout with at least one completed tapeout leading to silicon fabrication.
• Proficient using Cadence Virtuoso including Layout XL and constraint-driven design methodologies.
• Demonstrable understanding of parasitic effects in layout including techniques for matched pairs and critical nets.
• Basic knowledge of electromigration and IR drop considerations such as current density limits and power routing checks.
• Fundamentals of on-chip electromagnetics including coupling, shielding, and constraints for high-speed routing.
• Experience with physical verification tools such as Calibre or PVS for DRC/LVS and parasitic extraction tools like QRC or StarRC.
• Familiarity with scripting for layout automation using SKILL, Python, or both.
• Flexible to overlap working hours with teams in the US and India during critical tapeout phases.

Preferred Qualifications

• Layout experience in SiGe BiCMOS technology and knowledge of passive and isolation design techniques.
• Expertise in advanced FinFET CMOS layout at 7nm or smaller process nodes, including multi-patterning, coloring, and complex DRC adherence.
• Exposure to photonic IC layout practices including waveguide routing, curvilinear geometries, and photonics PDK rules.
• Experience with parametric photonic cell programming using Virtuoso SKILL or Python-based tools such as gdsfactory, KLayout, or IPKISS, including handling curvilinear-to-grid snapping and fracture strategies.
• Knowledge of silicon photonics components like Mach-Zehnder modulators, ring modulators, Germanium photodetectors, thermal phase shifters, and fiber coupling assembly sensitivities.
• Experience with 2.5D and 3D integration techniques including interposers, micro-bump and copper pillar array layouts.
• Layout experience on optical front-end blocks such as transimpedance amplifiers (TIA), modulator drivers, or high-speed serial links.

Why Join?

This position offers a unique opportunity to contribute to the emerging field of optical I/O for AI applications where layout quality directly dictates performance outcomes. You will take full ownership of circuit blocks from concept through tape-out and validation, gaining rare expertise in photonic layout engineering while growing into leadership roles within the layout and methodology domains.