Senior/Staff Process Engineer - Wafer Dicing and Back-grind

Job Overview

This role entails managing the silicon photonic wafer backside grinding and thinning processes, laser stealth dicing techniques, and die sorting development both internally and with OSAT partners to ensure high-quality silicon photonic chips.

Primary Duties

• Oversee wafer thinning thickness, grinding speed, cutting paths, and laser cutting parameters to prevent damages including chip cracks, edge chipping, and harm to sensitive optical structures on silicon photonic wafers.
• Address and troubleshoot process irregularities such as wafer warpage, surface scratches, incomplete cutting, and chip breakage during wafer thinning and dicing operations.
• Monitor uniformity of wafer thickness, quality of cutting, and production throughput; continuously refine processes to maximize product yield.
• Assess compatibility between wafer grinding/stealth dicing and downstream bumping & flip-chip processes to optimize integration and avoid failures caused by front-end variations.
• Document processes through SOPs, work instructions, failure reports, and engineering change notes; assist with new product introduction and process verification stages.

Qualifications and Experience

• Possess a Bachelor’s or Master’s degree in Materials Science, Chemical Engineering, Mechanical Engineering, Microelectronics, or a similar technical discipline.
• Hold at least 3 to over 6 years of practical experience in wafer process engineering, specializing in wafer mounting, dicing, thinning, or grinding—particularly with advanced packaging wafers featuring complex topology or stacking.
• Experience coordinating with external equipment and material suppliers to develop and qualify new tools and materials for assembly processes, leading to successful mass production ramp-up.
• Knowledgeable in statistical process control (SPC), JMP for data analytics, and design of experiments (DOE) matrix design to advance process development and use rigorous troubleshooting techniques.