ASIC Design Verification Engineer with UVM Expertise
Bengaluru, Karnataka, India · Full Time
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- Experience
- 5+ yrs
- Salary
- —
- Openings
- 1
- Posted
- 4 weeks ago
- Work mode
- In office
- Education
- Bachelor's degree or higher
- Resume
- Required to apply
Where you'll work
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Job description
Role Overview
Join Cisco as an ASIC Design Verification Engineer contributing to the development, design, and validation of ASICs and their subsystems that power various Cisco platforms. This role involves collaborating as part of a multidisciplinary engineering team to achieve power, performance, and area targets for products while delivering high-quality ASIC subsystems suitable for mass production. You will help to shape the processes, methodologies, and toolsets used in the design and implementation of complex ASIC projects.
Key Responsibilities
- Architect and develop verification environments for blocks, clusters, and top-level ASIC designs.
- Create new DV infrastructure from the ground up as well as maintain and optimize existing environments.
- Formulate comprehensive test plans incorporating both constraint-random and directed stimuli to thoroughly qualify designs across verification levels.
- Achieve full verification coverage through code and functional coverage reviews and implementation.
- Ensure RTL design quality by validating with gate-level simulations using netlists.
- Work closely with design, architecture, and software teams to troubleshoot and resolve issues during post-silicon bring-up activities.
- Support design testing in emulation platforms.
- Lead the entire ASIC bring-up process ensuring smooth integration and operation.
Qualifications
- Bachelor's degree plus seven or more years' ASIC design verification experience, or Master's degree plus five or more years.
- Strong proficiency in ASIC verification employing UVM and SystemVerilog methodologies.
- Demonstrated capability in verifying complex ASIC components at block, cluster, and top levels.
- Experience constructing test benches from scratch, including hands-on with SystemVerilog constraints, data structures, and classes.
- Scripting expertise in Perl and/or Python.
Preferred Skills
- Knowledge of forwarding logic, packet parsers, and P4 programming.
- Familiarity with emulation tools such as Veloce, Palladium, Zebu, and HAPS.
- Experience with formal verification tools (iev, vc formal).
- Expertise in one or more protocols like PCIe, Ethernet, RDMA, or TCP.
About Cisco
Cisco has been a global leader in connecting and securing digital infrastructure for over four decades, driving innovation in AI and beyond. The company prides itself on offering groundbreaking technologies that provide unmatched security, insight, and visibility across digital footprints globally. Cisco fosters a collaborative culture fueled by technological depth and a global network of experts, offering opportunities for significant professional growth and impactful global contributions.
Minimum education
Bachelor's Degree