Verification Engineer

About the Role and Company

At Ubitium, the belief is that the best engineering emerges when diverse perspectives come together to solve challenging problems. They seek curious, skilled, and motivated individuals passionate about building technology that positively impacts the world. The team consists of members from prestigious universities and top tech companies, aiming to create something exceptional.

Key Responsibilities

• Create testbenches using cocotb for RTL blocks, ranging from complex datapaths to multi-level interconnects, driven primarily by property-based test generation instead of static directed vectors.
• Develop SystemVerilog Assertions (SVA) to detect protocol violations during simulation and implement cover properties to address functional coverage gaps.
• Perform cross-validation of RTL behavior against independent golden reference models, including formally specified ones, to identify discrepancies between specification intent and implementation.
• Lead efforts to close functional coverage by reviewing and analyzing coverage reports.
• Investigate failures using waveform viewers and simulator logs to trace problems from failed assertions or model mismatches back to their root causes in RTL, testbenches, or models.
• Document and manage outstanding verification issues such as RTL bugs, model deficiencies, or verification methodology limitations with comprehensive reproduction steps to ensure clarity and collaborative resolution.
• Contribute to continuous enhancement of the verification infrastructure, including build automation, test harnesses, and coverage tools.

Candidate Requirements

• Proficiency in SystemVerilog, including writing SystemVerilog Assertions, and Python programming.
• Experience with RTL debugging, property-based verification methodologies, and version control systems such as Git.
• Exposure to formal verification techniques is a plus.
• Possession of a Master’s degree or equivalent, accompanied by more than 2 years of practical experience in related verification roles.
• Willingness to relocate is mandatory. Currently, the working arrangement includes 4 days onsite, 1 day remote, though this may change.

Benefits and Culture

• Opportunity to influence and develop the verification methodology rather than just executing predefined tasks.
• Direct collaboration with architects and designers, enabling your findings and root cause analysis to actively shape RTL development and improvement.
• Exposure to the entire technology stack of a RISC-V System on Chip (SoC).
• Competitive remuneration packages including salary and stock options.
• Generous leave policy offering over 30 days of paid vacation annually.
• Support for relocation and full coverage under the German social security and universal healthcare systems.
• A modern office environment with complimentary snacks, coffee, and drinks.
• A team comprising experts in computer architecture and hardware engineering fostering a culture of respect, collaboration, and innovation.
• Opportunities for personal growth by acquiring new skills and exploring areas of interest.
• Practical involvement with real AI and signal processing implementations beyond theoretical concepts.
• An inclusive environment valuing diverse viewpoints and encouraging contribution from all members.

Additional Information

The recruitment process involves multiple pathways including referrals, academic connections, recruiters, industry events, and outreach programs. The organization welcomes applications from all qualified individuals interested in joining their dynamic team.