Senior Staff DFT Engineer

About the Company

We are pioneers in advancing high-performance computing through our innovative coprocessor, which significantly accelerates supercomputers, ushering in a new era of computing power. Our software-defined hardware architecture empowers HPC to deliver ground-breaking outcomes across diverse research domains. Our core values include professionalism, unity, and making a meaningful impact worldwide.

Role Overview

We seek an experienced Design for Test (DFT) Engineer to lead the implementation of DFT strategies for our next-generation system-on-chip (SoC). This role is critical within the semiconductor and electronics sectors, emphasizing the design and integration of testing solutions to guarantee the functionality, reliability, and manufacturability of integrated circuits through their entire product lifecycle.

Responsibilities

• Establish and define DFT architecture and methodologies tailored for next-generation SoC designs.
• Implement scan chain, MBIST, and boundary scan techniques ensuring alignment with architectural specifications.
• Create comprehensive test routines to validate DFT capabilities in both RTL and gate-level simulations including timing and no-timing scenarios.
• Evaluate fault models and enhance coverage metrics covering stuck-at faults, transition faults, path delay, IDDQ, among others.
• Collaborate closely with multifunctional teams to design, verify, and constrain DFT structures effectively.
• Liaise with Test Engineering teams to support test programming, silicon bring-up, fault diagnosis, and yield enhancement activities.

Qualifications and Requirements

• Minimum 8 years of hands-on experience in DFT methodology and implementation.
• Strong foundation in digital design principles and comprehensive test methodologies.
• Expertise in advanced DFT techniques including scan compression, SSN, scan stitching, and fault modeling such as stuck-at, delay tests, IDDQ, small delay; familiarity with IEEE P1500, MBIST, IEEE 1149.1/6 boundary scan, and IEEE 1687 standards.
• Proficient use of industry-leading EDA tools such as Synopsys Fusion Compiler, TestMax, and Mentor Tessent alongside scripting proficiency in Python, TCL, and Makefile.
• Solid understanding of IC design flows, verification tools, and file formats such as SDC.
• Excellent problem-solving skills to identify and resolve testing complexities effectively.
• Demonstrated success in developing complex custom ASIC products, particularly in advanced process nodes, including multiple tapeouts.
• Self-driven team player capable of collaborating across diverse teams while communicating intricate technical information clearly.