Senior STA Lead

Job Overview

We are looking for an experienced Senior Static Timing Analysis (STA) Lead to spearhead the timing analysis strategy for cutting-edge CPU projects operating above 3GHz. This role involves leading project execution, owning the sign-off process, and collaborating extensively with diverse teams to achieve flawless first silicon.

Key Responsibilities

• Manage full-chip and block-level static timing sign-off using industry tools such as PrimeTime and PrimeClosure while establishing sign-off criteria and checklists.
• Design and implement sophisticated timing analysis methodologies and flows including OCV/POCV, MMMC, hierarchical timing, and automating sign-off tasks.
• Lead the resolution of intricate timing closure issues, accommodating DVFS, high-frequency datapaths, complex clocking domains, and asynchronous systems.
• Collaborate closely with Architecture, RTL, DFT, Analog, and Physical Design teams to provide early-stage feedback on micro-architecture, timing budgets, and optimization of power and area tradeoffs.
• Conduct thorough technical reviews, assess sign-off preparedness, and formulate risk reduction plans.
• Promote automation and workflow optimization through scripting using TCL and Python for timing analysis, ECO generation, and Quality of Results tracking.
• Stay updated on industry innovations, EDA tool enhancements, and best practices to continuously advance STA methodologies and team skills.

Qualifications

• Master’s or Bachelor’s degree in Electronics, Electrical Engineering, Computer Engineering, or a related field.
• Over 10 years of static timing analysis experience in CPU, ASIC, or SoC domains, including at least 3 years in a technical leadership capacity.
• Extensive proficiency with STA tools like PrimeTime, SDC constraints, and advanced timing techniques such as OCV/POCV and MMMC.
• Demonstrated success in achieving timing closure and silicon sign-off on complex projects.
• Strong scripting capabilities in TCL and Python aimed at automating flows and analyzing data.
• Excellent leadership, communication, and collaboration skills across multiple disciplines.
• Experience in mentoring and developing engineers.

Preferred Experience

• Familiarity with advanced semiconductor process technologies (7nm, 5nm, or below).
• Knowledge of low-power design standards, including UPF and CPF methodologies.
• Exposure to physical design, synthesis methodologies, and Design for Test (DFT) flows.
• Experience working with global, distributed teams.