Senior ISP RTL Design Manager

Role Overview

This position focuses on translating Image Signal Processing (ISP) algorithms into hardware implementations using Verilog, SystemVerilog, and SystemC (High Level Synthesis). The role entails defining hardware architecture for ISP based on desired product features, performance targets, and constraints such as gate count and power consumption.

Key Responsibilities

• Implement ISP algorithms in hardware describing languages like Verilog, SystemVerilog, and SystemC.
• Establish ISP hardware architecture encompassing performance objectives, gate count, and power budget estimations.
• Conduct verification of ISP logic at the module and complete digital system levels.
• Enhance designs aiming to minimize gate usage and reduce power consumption.
• Lead ISP design efforts collaborating closely with ISP algorithm teams, design leads across sites, and digital system design teams.
• Provide leadership, supervision, and mentorship to a group of RTL design engineers.

Required Qualifications and Skills

• Master’s or Bachelor’s degree in Electrical Engineering or equivalent field with over 7 years of experience in digital design and verification.
• At least 3 years of experience in project or people management roles.
• Expertise or demonstrated knowledge in CMOS image sensors and image signal processing.
• Proficiency with SystemC/C++, SystemVerilog, and Catapult High-Level Synthesis tools.
• Strong leadership capabilities and ability to collaborate across multiple functions.
• Excellent time management to ensure project milestones are met punctually.
• Effective communication and interpersonal skills.
• Results-driven mindset with adaptability to change.