Senior ISP RTL Design Manager

Role Overview

The Senior ISP RTL Design Manager is responsible for transforming ISP algorithms into hardware implementations using Verilog, SystemVerilog, and SystemC technologies, including High-Level Synthesis. This role involves defining ISP hardware architecture aligned with product capabilities, performance targets, gate count, and power consumption estimations.

Key Responsibilities

• Translate ISP algorithms into hardware designs with Verilog, SystemVerilog, and SystemC (HLS).
• Architect ISP hardware by evaluating product features along with performance, gate count, and power budgets.
• Conduct verification of logic at both ISP and comprehensive digital system levels.
• Refine designs to reduce gate count and optimize power efficiency.
• Lead and coordinate ISP design initiatives, working closely with ISP algorithm teams, peer design leaders across locations, and digital system design departments.
• Supervise, lead, and mentor a team of RTL design engineers to ensure technical and project delivery excellence.

Candidate Requirements

• Possess a minimum of Masters or Bachelors degree in Electrical Engineering or an equivalent field alongside over 7 years of experience in digital design and verification.
• At least 3 years of demonstrated project or people management expertise.
• Familiarity with CMOS Image Sensor technology and image signal processing concepts.
• Proficiency in SystemC/C++, SystemVerilog, and usage of Catapult High-Level Synthesis tools.
• Strong leadership qualities with the capacity to manage cross-functional teams effectively.
• Excellent time management skills aimed at meeting project deadlines.
• Effective communication skills coupled with strong interpersonal abilities.
• Outcome-driven mindset and adaptability to change.