Senior DFT Engineer

Overview

We are looking for a proactive Senior Design-for-Test (DFT) Engineer to join our SoC/ASIC DFT development group based in Yishun, Singapore. This role entails hands-on responsibility for developing and validating DFT solutions on complex hierarchical designs to achieve first-pass silicon success. The engineer will work closely with physical design teams and Automated Test Equipment (ATE) test groups to devise and implement efficient and industry-compliant test methodologies.

Key Responsibilities

• Create and deploy DFT architectures for hierarchical SoC and ASIC designs, managing block and top-level DFT integration.
• Conduct scan and test point insertion along with test compression using Serial Stream Network (SSN) or similar compression architectures.
• Validate SSN topology, handling scan chain balancing and clock domain crossings effectively.
• Integrate Boundary Scan (IEEE 1149.x) and other test access methods to enhance chip-level testability.
• Generate and evaluate ATPG patterns targeting stuck-at, transition, and path delay faults to maximize test coverage.
• Execute DFT verification through Verilog and gate-level simulations.
• Collaborate with cross-functional teams to address DFT and testing timing issues.
• Work with ATE engineers to prepare and verify timing and pattern files (such as STIL/WGL) ensuring compatibility with test equipment and readiness for production.
• Provide support during silicon bring-up and production testing, including diagnostics and failure analysis.

Qualifications

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related discipline.
• A minimum of 3 years' experience in DFT design and verification, with preference for candidates holding 5 or more years for senior-level roles.
• Strong knowledge of scan-based testing techniques, test compression, hierarchical DFT methods.
• Experience utilizing DFT tools like Siemens Tessent.
• Expertise in ATPG generation, fault coverage metrics, and gate-level DFT validation.
• Understanding of ATE test flows and pattern validation on platforms such as Advantest or Teradyne.
• Proficient scripting skills in TCL, Perl, or Python to automate DFT workflows.