IC Layout Engineer

Role Overview

This position involves delivering high-quality IC layouts for Standard Cells, I/O pads, and Mixed-Signal IP using advanced semiconductor processes within defined project timelines.

Key Responsibilities

• Design and implement layouts adhering to design rules and process guidelines to ensure robust and high-performance circuits.
• Plan and manage layout activities from transistor-level design through cell- and block-level floorplanning according to schedule.
• Collaborate effectively by adopting innovative approaches, maintaining communication across different sites, and working closely with senior engineers.

Required Skills and Qualifications

• Bachelor's degree in Electronic Engineering.
• 2 to 3 years of practical experience in IC layout design.
• Fundamental knowledge of Standard Cell, Memory, or Analog/Mixed-Signal layout design principles.
• Awareness of ESD and Latch-up layout protection methods and transistor-level placement techniques.
• Experience with physical verification procedures including Design Rule Check (DRC), Layout Versus Schematic (LVS), Electrical Rule Check (ERC), and Antenna effect assessments.
• Basic familiarity with advanced sub-micron semiconductor technologies such as 5nm, 3nm, 2nm, or 1.4nm process nodes.
• Competency in using Cadence Virtuoso for layout and Mentor Calibre tools for physical verification (DRC, LVS, ERC, Antenna, Electromigration/IR drop analysis).
• Programming skills in scripting languages like Shell, Python, Tcl, or Cadence SKILL scripting are advantageous.
• Demonstrates a proactive attitude, rapid learning ability, teamwork spirit, strong problem-solving aptitude, and effective communication skills.

Additional Information

Job Code: R026654