Senior CPU Design Verification Engineer

About SiFive

SiFive pioneered the introduction of RISC-V architecture globally and is revolutionizing computing by extending RISC-V's possibilities into high-performance, data-intensive markets. Its computing platforms are pivotal to leading tech firms innovating in chip design domains including AI, machine learning, automotive, data centers, mobile, and consumer electronics, enabling cutting-edge, advanced solutions.

At SiFive, collaboration and a passion for innovation drive teams to develop impactful, world-changing processor technologies. The company has received recognition such as the GSA's Most Respected Private Company Award multiple times.

Position Overview

The role focuses on leading verification efforts at block and subsystem levels for sophisticated out-of-order CPU cores. The engineer will collaborate closely with micro-architects and RTL designers to test and validate intricate execution pipelines, memory structures, and coherence protocols utilizing modern, coverage-driven verification methodologies.

Key Responsibilities

• Lead verification for crucial out-of-order CPU components including front-end stages (fetch, branch prediction, decode), rename and register mapping, issue queues/schedulers and execution, reorder buffer and retirement mechanisms, load-store units with atomics and fences, as well as L1 caches, TLBs, MMU, and coherence interfaces.
• Create comprehensive verification plans derived from architecture and micro-architecture documents, emphasizing speculative execution dynamics, pipeline hazard detection, memory ordering, consistency models, and cache-coherence interactions.
• Develop and maintain SystemVerilog/UVM testbenches, including agents, monitors, scoreboards, and reference models to generate constrained-random and directed tests targeting complex out-of-order corner cases.
• Implement self-checking features for instruction retirement, architectural state, memory ordering, atomics, fences, TLB, page-table walks, and privilege/protection sequences.
• Define and monitor functional, code, and assertion coverage metrics; identify coverage gaps and augment tests and monitors accordingly.
• Craft and maintain SystemVerilog Assertions (SVA) validating critical micro-architectural properties such as deadlock absence, correct handling of mispredictions, exceptions, interrupts, flush paths, and pipeline data forwarding and hazard resolutions.
• Analyze regression outputs, troubleshoot failures, and collaborate with design and architecture teams to drive issues to resolution.
• Debug complex problems involving speculation logic, load-store ordering, memory consistency, and TLB/MMU corner cases.
• Work closely with micro-architecture and RTL design teams for fixes and clarification, with performance/modeling groups to ensure alignment, and with post-silicon validation teams for issue correlation.
• Contribute to verification methodology enhancements, including UVM components, coverage approaches, and regression routines.
• Mentor junior engineers through guidance and code reviews on testbench design, stimulus generation, and debugging.

Qualifications and Experience

• Academic Credentials: Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or related disciplines.
• Professional Experience: Typically 5 to 10 years in ASIC, SoC, or IP design verification.
• Direct background in verification of out-of-order or superscalar CPU cores or similarly complex high-performance pipelines is essential.
• Technical Proficiency: Advanced knowledge of SystemVerilog and UVM or equivalent methodologies; deep understanding of CPU micro-architecture components including fetch/decode, rename, reorder buffer, issue/execute stages, bypassing, and commit phases.
• Familiarity with load-store units, atomics, fences, memory ordering, L1 caches, TLBs, page-table walkers, and foundational cache coherence concepts.
• Hands-on skills in constrained-random and coverage-driven verification, writing and debugging SystemVerilog Assertions, and usage of simulators such as VCS, Xcelium, and Questa alongside debug tools like Verdi or DVE.
• Strong problem-solving ability for complex corner-case defects and effective communication skills for cross-team collaboration.
• Capacity to manage complex block-level tasks independently while contributing to broader project goals.

Additional Information

Employment is subject to satisfactory background and reference checks and verification of your legal right to work in India.

Offers depend on verification of authorization to access export-controlled technology under applicable laws or successful obtaining of required export licenses or approvals if not already authorized.

SiFive is committed to equal employment opportunities, valuing diversity, and fostering an inclusive workplace environment.